12032IVZ データシートの表示（PDF） - Renesas Electronics

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12032IVZ

Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Crystal Back-up

Renesas Electronics 

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

Brownout Detection

The ISL12032 monitors the VDD level continuously and

provides a warning if the VDD level drops below prescribed

levels. There are six levels that can be selected for the trip

level. These values are 85% below popular VDD levels. The

LVDD bit in the SRDC register will be set to “1” when Brownout

is detected. Note that the I2C serial bus remains active until the

Battery VTRIP level is reached.

Battery Level Monitor

The ISL12032 has a built in warning feature once the VBAT

battery level drops first to 85% and then to 75% of the battery’s

nominal VBAT level. When the battery voltage falls to between

85% and 75%, the LBAT85 bit is set in the SRDC register.

When the level drops below 75%, both LBAT85 and LBAT75

bits are set in the SRDC register. The trip levels for the 85%

and 75% levels are set using the PWRBAT register.

The Battery Timestamp Function permits recovering the

time/date when VDD power loss occurred. Once the VDD is low

enough to enable switchover to the battery, the RTC time/date

are written into the TSV2B section. If there are multiple power-

down cycles before reading these registers, the first values

stored in these registers will be retained and ensuing events

will be ignored. These registers will hold the original power-

down value until they are cleared by writing “00h” to each

register or setting the CLRTS bit to “1”.

The VDD Timestamp Function permits recovering the time/date

when VDD recovery occurred. Once the VDD is high enough to

enable switchover to VDD, the RTC time/date are written into

the TSB2V register. If there are multiple power-down cycles

before reading these registers, the most recent event is

retained in these registers and the previous events will be

ignored. These registers will hold the original power-down

value until they are cleared by writing “00h” to each register.

Real Time Clock Operation

The Real Time Clock (RTC) maintains an accurate internal

representation of tenths of a second, second, minute, hour, day

of week, date, month, and year. The RTC also has leap-year

correction. The clock also corrects for months having fewer

than 31 days and has a bit that controls 24 hour or AM/PM

format. When the ISL12032 powers up after the loss of both

VDD and VBAT, the clock will not begin incrementing until at

least one byte is written to the clock register.

Alarm Operation

The alarm mode is enabled via the MSB bit. Single event or

interrupt alarm mode is selected via the IM bit. The standard

alarm allows for alarms of time, date, day of the week, month,

and year. When a time alarm occurs in single event mode, the

IRQ pin will be pulled low and the corresponding alarm status

bit (ALM0 or ALM1) will be set to “1”. The status bits can be

written with a “0” to clear, or if the ARST bit is set, a single

read of the SRDC status register will clear them.

The pulsed interrupt mode (setting the IM bit to “1”) activates a

repetitive or recurring alarm. Hence, once the alarm is set, the

device will continue to output a pulse for each occurring match

of the alarm and present time. The Alarm pulse will occur as

often as every minute (if only the nth second is set) or as

infrequently as once a year (if at least the nth month is set).

During pulsed interrupt mode, the IRQ pin will be pulled LOW

for 250ms and the alarm status bit (ALM0 or ALM1) will be set

to “1”.

The alarm function is not available during battery backup

mode.

Frequency Output Mode

The ISL12032 has the option to provide a clock output signal

using the FOUT CMOS output pin. The frequency output mode

is set by using the FO bits to select 7 possible output frequency

values from 1.0Hz to 32.768kHz, and disable. The frequency

output can be enabled/disabled during battery backup mode by

setting the FOBATB bit to “0”. When the AC input is qualified

(within the parameters of AC qualification) then the Frequency

Output for values 50/60Hz and below are derived from the AC

input clock. Higher frequency FOUT values are derived from

the crystal. If the AC clock input is not qualified, then all FOUT

values are derived from the crystal.

General Purpose User SRAM

The ISL12032 provides 128 bytes of user SRAM. The SRAM

will continue to operate in battery backup mode. However, it

should be noted that the I2C bus is disabled in battery backup

mode unless enabled by the I2CBAT bit.

I2C Serial Interface

The ISL12032 has an I2C serial bus interface that provides

access to the control and status registers and the user SRAM.

The I2C serial interface is compatible with other industry I2C

serial bus protocols using a bi-directional data signal (SDA)

and a clock signal (SCL).

The I2C bus normally operates down to the VDD trip point set

in the PWRVDD register. It can also operate in battery backup

mode by setting the I2CBAT bit to “1”, in which case operation

will be down to VBAT = 1.8V.

Register Descriptions

The battery-backed registers are accessible following an I2C

slave byte of “1101 111x” and reads or writes to addresses

[00h:47h]. The defined addresses and default values are

described in the Table 1. The battery backed general purpose

SRAM has a different slave address (1010 111x), so it is not

possible to read/write that section of memory while accessing

the registers.

REGISTER ACCESS

The contents of the registers can be modified by performing a

byte or a page write operation directly to any register address.

The registers are divided into 10 sections. They are:

FN6618 Rev 3.00

May 5, 2011

Page 10 of 26

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