12032IVZ データシートの表示（PDF） - Renesas Electronics

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12032IVZ

Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Crystal Back-up

Renesas Electronics 

ISL12032 Real Time Clock with 50/60 Hz clock and Crystal Backup

DC Operating Characteristics Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface

limits apply over the operating temperature range, -40°C to +85°C. (Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

(Note 13) (Note 7) (Note 13) UNITS

NOTES

VTRKHYS Trickle Charge ON-OFF Hysteresis

50

mV

IRQ/ACRDY/LV/EVDET (OPEN DRAIN OUTPUTS)

VOL

Output Low Voltage

FOUT (CMOS OUTPUT)

VOL

Output Low Voltage

VOH

Output High Voltage

EVIN

VDD = 5V, IOL = 3mA

VDD = 2.7V, IOL = 1mA

IOH = 1mA

0.7 x VDD

0.4

V

0.4

V

0.3 x VDD

V

V

IEVPU

VIL

VIH

IEVPD

EVIN Pull-up Current

VDD = 5.5V, VBAT = 3.0V

1.0

3.0

8.0

µA

VDD = 0V, VBAT = 1.8V

100

600

nA

Input Low Voltage

0.3 x VDD

V

Input High Voltage

0.7 x VDD

V

EVIN Disabled Pull-down Current VDD = 5.5V

200

nA

Power-Down Timing Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits apply over

the operating temperature range, -40°C to +85°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

(Note 13) (Note 7) (Note 13) UNITS

NOTES

VDD SR-

VDD Negative Slew Rate

10

V/ms

9

I2C Interface Specifications Specifications apply for: VDD = 2.7V to 5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits

apply over the operating temperature range, -40°C to +85°C.

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

(Note 13) (Note 7) (Note 13) UNITS NOTES

VIL

SDA and SCL Input Buffer LOW

Voltage

VIH

SDA and SCL Input Buffer HIGH

Voltage

-0.3

0.7 x VDD

0.3 x VDD V

VDD + 0.3 V

Hysteresis

SDA and SCL Input Buffer

Hysteresis

0.05 x VDD

V

VOL

CPIN

fSCL

tIN

tAA

SDA Output Buffer LOW Voltage,

Sinking 3mA

SDA and SCL Pin Capacitance

SCL Frequency

Pulse Width Suppression Time at

SDA and SCL Inputs

SCL Falling Edge to SDA Output

Data Valid

VDD = 5V, IOL = 3mA

TA = +25°C, f = 1MHz,

VDD = 5V, VIN = 0V,

VOUT = 0V

Any pulse narrower than the

max spec is suppressed.

SCL falling edge crossing

30% of VDD, until SDA exits

the 30% to 70% of VDD

window.

0.4

V

10

pF

400

kHz

50

ns

900

ns

tBUF

Time the Bus Must be Free Before SDA crossing 70% of VDD

1300

ns

the Start of a New Transmission during a STOP condition, to

SDA crossing 70% of VDD

during the following START

condition.

FN6618 Rev 3.00

May 5, 2011

Page 5 of 26

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