UPA675T データシートの表示（PDF） - TY Semiconductor

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UPA675T

Two MOS FET circuits in package the same size as SC-70

TY Semiconductor 

Product specification

µ PA675T

ELECTRICAL CHARACTERISTICS (TA = 25°C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

Zero Gate Voltage Drain Current

IDSS

VDS = 16 V, VGS = 0 V

Gate Leakage Current

IGSS

VGS = ±7.0 V, VDS = 0 V

Gate Cut-off Voltage

VGS(off) VDS = 3 V, ID = 10 µA

Forward Transfer Admittance

| yfs | VDS = 3 V, ID = 10 mA

Drain to Source On-state Resistance

RDS(on)1 VGS = 1.5 V, ID = 1 mA

RDS(on)2 VGS = 2.5 V, ID = 10 mA

RDS(on)3 VGS = 4.0 V, ID = 10 mA

Input Capacitance

Ciss

VDS = 3 V

Output Capacitance

Coss

VGS = 0 V

Reverse Transfer Capacitance

Crss

f = 1 MHz

Turn-on Delay Time

td(on)

VDD = 3 V, ID = 10 mA

Rise Time

tr

VGS = 3 V

Turn-off Delay Time

td(off)

RG = 10 Ω

Fall Time

tf

MIN. TYP. MAX. UNIT

1.0 µA

±3.0 µA

0.5 0.8 1.1 V

20

mS

20 50

Ω

7

15

Ω

5

12

Ω

10

pF

13

pF

3

pF

15

ns

70

ns

100

ns

110

ns

SWITCHING TIME MEASUREMENT CIRCUIT AND CONDITIONS

PG.

RG

VGS

0

τ

τ = 1 µs

Duty Cycle ≤ 1%

DUT

RL

VDD

Gate

Voltage

Wave-

form

Drain

Current

Wave-

form

VGS

VGS

0 10%

ID

90%

ID

10%

0

td(on)

tr td(off)

90%

90%

10%

tf

ton

toff

http://www.twtysemi.com

sales@twtysemi.com

4008-318-123

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