UPD16707A データシートの表示（PDF） - NEC => Renesas Technology
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UPD16707A Datasheet PDF : 13 Pages
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µ PD16707A
3. PIN FUNCTIONS
Pin Symbol
Pin Name
I/O
Description
O1 to O263 Driver
Output These pins output scan signals that drive the vertical direction (gate lines) of a TFT-LCD.
The output signals change in synchronization with the rising edge of shift clock CLK.
The driver output amplitude is VDD2-VEE.
O0, O264
R,/LR,
R,/LL
Driver
Shift direction
control
Output
Input
The signal of VEE level is outputted by fixation.
The shift direction control pin of shift register.
R,/LR, R,/LL = H (right shift): STVR → O1 → O263 → STVL
R,/LR, R,/LL = L (left shift): STVL → O263 → O1 → STVR
R,/LR and R,/LL are connected inside IC.
★ STVR,
Start pulse
I/O This is the I/O of the internal shift register. The start pulse is read at the rising edge of shift
STVL
clock CLK (CLKR, CLKL), and scan signals are output from the driver output pins. The
input level is a VDD1-VSS (logic level). When in MODE = H, the start pulse is output at the
falling edge of the 263rd clock of shift clock CLK, and is cleared at the falling edge of the
264th clock.
The output level is VDD1-VSS (logic level).
CLKR,
CLKL
Shift clock
Input This pin inputs a shift clock to the internal shift register. The shift operation is performed in
synchronization with the rising edge of this input. CLKR and CLKL are connected inside IC.
OER, OEL Output enable
Input When this pin goes high level, the driver output is fixed to VEE level.
The shift register is not cleared. CLK is asynchronous in the clock.
OER and OEL are connected inside IC.
/AOR,
/AOL
All-on control
Input When this pin goes low level, all driver output = VDD2 level.
The shift register is not cleared. This pin has priority over OER and OEL.
This pin is pulled up to VDD1 power supply inside IC.
CLK is asynchronous in the clock.
/AOR and /AOL are connected inside IC.
MODE
Selection of number
of outputs
Input
MODE = VDD1 or open: 263 outputs
MODE = VSS: 256 outputs (Driver pins O129 to O135 are invalid.)
Input level is VDD1-VSS (logic level)
This pin is pulled up to VDD1 power supply inside IC.
VDD1
Logic power supply
– 2.3 to 3.6 V
VDD2
Driver positive
power supply
– 5 to 30 V. The driver output: High level
VSS
Logic ground
– Connect this pin to the ground of the system.
VEE
Negative Power
– −15 to −3 V. The driver output: Low level
supply for internal
operation
Cautions 1. To prevent latch-up, turn on power to VDD1→VEE→VDD2→logic input in this order. Turn off power in
the reverse order. These power up/down sequence must be observed also during
transition period.
2. Insert a capacitor of about 0.1 µF between each power line, as shown below, to secure noise
margin such as VIH and VIL.
VDD2
VDD1
VSS
VEE
0.1 µF
0.1 µF
0.1 µF
4
Data Sheet S16563EJ1V0DS
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