A625308A_06 データシートの表示（PDF） - AMIC Technology

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A625308A_06

32K X 8 BIT CMOS SRAM

AMIC Technology 

Timing Waveforms (continued)

Read Cycle 3 (1, 3, 4)

A625308A Series

CE

DOUT

tCLZ 5

tACE

tCHZ 5

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled, CE = VIL.

3. Address valid prior to or coincident with CE transition low.

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

Write Cycle 1 (6)

(Write Enable Controlled)

Address

CE

WE

DIN

DOUT

(4)

tAS1

tWC

tAW

tCW5

tWP2

tWR3

tDW

tWHZ 7

tDH

tOW 7

(September, 2006, Version 1.3)

7

AMIC Technology, Corp.

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