ISL5861 データシートの表示（PDF） - Renesas Electronics
部品番号
コンポーネント説明
メーカー
ISL5861 Datasheet PDF : 14 Pages
| |||
ISL5861
REQ = 0.5 x (RLOAD // RDIFF)
AT EACH OUTPUT
PIN 21
PIN 22
ISL5861
IOUTB
RDIFF
IOUTA
VOUT = (2 x IOUTA x REQ)V
1:1
RLOAD
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
REQ = 0.5 x (RLOAD // RDIFF// RA), WHERE RA=RB
AT EACH OUTPUT
PIN 21
PIN 22
ISL5861
IOUTB
IOUTA
RA
RDIFF
RB
VOUT = (2 x IOUTA x REQ)V
RLOAD
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 14. ALTERNATIVE OUTPUT LOADING
Timing Diagram
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous data.
The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form. The form can be found by doing an ‘entire site
search’ at www.intersil.com on the words ‘DAC Testdrive’. Or,
send a request to the technical support center.
CLK
D11-D0
IOUT
tPW1
tPW2
tSU
W0
tHLD
tSU
W1
tPD
tHLD
tSU
W2
tPD
OUTPUT=W0
tHLD
50%
W3
OUTPUT=W-1
OUTPUT=W1
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
FN6008 Rev 3.00
Oct 7, 2015
Page 11 of 14
Share Link: 