ISL85415FRZ-T7A データシートの表示（PDF） - Renesas Electronics
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ISL85415FRZ-T7A Datasheet PDF : 31 Pages
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ISL85415
Pin Number
5
6
7
8
9
10
11
12
EPAD
1. Overview
Pin Name
PHASE
PGND
EN
PG
VCC
FB
COMP
FS
GND
Description
Switch node output. It connects the switching FET’s with the external output inductor.
Power ground connection. Connect directly to the system GND plane.
Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground.
When the voltage on this pin rises above 1V, the chip is enabled. Connect this pin to VIN for
automatic start-up. Do NOT connect EN pin to VCC since the LDO is controlled by EN voltage.
Open-drain power-good output that is pulled to ground when the output voltage is below regulation
limits or during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.
Output of the internal 5V linear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at
the pin.
Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is
the output of the error amplifier. The output voltage is set by an external resistor divider connected
to FB. In addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the
regulator output voltage.
COMP is the output of the error amplifier. When it is tied to VCC, internal compensation is used.
When only an RC network is connected from COMP to GND, external compensation is used. See
“Loop Compensation Design” on page 25 for more details.
Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for
adjustable frequency from 300kHz to 2MHz.
Signal ground connections. Connect to application board GND plane with at least five vias. All
voltage levels are measured with respect to this pin. The EPAD MUST NOT float.
FN8373 Rev.5.01
Jun.4.20
Page 6 of 30
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