HSP43220JC-33 データシートの表示（PDF） - Renesas Electronics
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HSP43220JC-33 Datasheet PDF : 21 Pages
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HSP43220
Block Diagram
Pinout
DECIMATION UP TO 1024 DECIMATION UP TO 16
INPUT CLOCK
DATA INPUT 16
CONTROL AND COEFFICIENTS 16
HIGH ORDER
DECIMATION
FILTER
FIR
DECIMATION
24
DATA OUT
FILTER
DATA READY
FIR CLOCK
HSP43220
84 PLASTIC LEADED CHIP CARRIER (PLCC)
TOP VIEW
STARTOUT
VCC
STARTIN
ASTARTIN
RESET
A1
A0
WR
CS
C_BUS 15
C_BUS 14
C_BUS 13
C_BUS 12
C_BUS 11
C_BUS 10
C_BUS 9
VCC
GND
C_BUS 8
C_BUS 7
C_BUS 6
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
74
13
73
14
72
15
71
16
70
17
69
18
68
19
67
20
66
21
65
22
64
23
63
24
62
25
61
26
60
27
59
28
58
29
57
30
56
31
55
32
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
GND
DATA_OUT 0
DATA_OUT 1
DATA_OUT 2
DATA_OUT 3
DATA_OUT 4
DATA_OUT 5
DATA_OUT 6
DATA_OUT 7
DATA_OUT 8
DATA_OUT 9
DATA_OUT 10
DATA_OUT 11
GND
VCC
DATA_OUT 12
DATA_OUT 13
DATA_OUT 14
DATA_OUT 15
DATA_OUT 16
DATA_OUT 17
Pin Description
NAME TYPE
DESCRIPTION
VCC
GND
The +5V power supply pins.
The device ground.
CK_IN
I Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this clock signal. The maximum clock
frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks may be tied together if required, or CK_IN
can be divided down from FIR_CK. CK_IN is a CMOS level signal.
FIR_CK
I Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the
rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal.
FN2486 Rev 10.00
Oct 10, 2008
Page 2 of 21
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