HSP43220JC-33 データシートの表示（PDF） - Renesas Electronics
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HSP43220JC-33 Datasheet PDF : 21 Pages
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HSP43220
COMB_EN5
COMB_EN4
COMB_EN3
COMB_EN2
COMB_EN1
FROM
DECIMATION
REGISTER
RESET
REG
26
B A-B
A
22
RESET
REG
B A-B
A
21
RESET
REG
B A-B
19 A
20
RESET
REG
B A-B
A
19
RESET
REG
TO
ROUNDER
B A-B
A
CK_DEC
FIGURE 3. COMB FILTER
Comb Filter Section
The output of the Decimation Register is passed to the
Comb Filter Section. The Comb section consists of 5
cascaded Comb filters or differentiators. Each Comb filter
section calculates the difference between the current and
previous integrator output. Each Comb filter consists of a
register which is clocked by CK_DEC, followed by an
subtractor, where the subtractor calculates the difference
between the input and output of the register. Bit truncations
are done at each stage as shown in Figure 3. The first
stage bit width is 26 bits and the output of the fifth stage is
19 bits.
There are three signals that control the Comb Filter;
H_STAGES, H_BYP and RESET. In Figure 3 these control
signals are decoded as COMB_EN1 - COMB_EN5. The
order of the Comb filter is controlled by H_STAGES, which is
programmed over the control bus. H_BYP is used to put the
comb section in bypass mode. RESET causes the register
output in each Comb stage to be cleared. The H_ BYP and
RESET control pins, when asserted force the output of all
registers to zero so data is passed through the subtractor
unaltered. When the H_STAGES control bits enable a given
stage the output of the register is subtracted from the input.
It is important to note that the Comb filter section has a speed
limitation. The Input sampling rate divided by the decimation
factor in the HDF (CK_IN/HDEC) should not exceed 4MHz.
Violating this condition causes the output of the filter to be
incorrect. When the HDF is put in bypass mode this limitation
does not apply. Equation 2 describes the relationship between
F_TAPS, F_DRATE, H_DRATE, CK_IN and FIR_CK.
filter stage in the HDF section has a 16-bit integer portion
with a 3-bit fractional part in 2's complement format.
The rounding algorithm is as follows:
POSITIVE NUMBERS
Fractional Portion to 0.5
Fractional Portion < 0.5
NEGATIVE NUMBERS
Fractional Portion 0.5
Fractional Portion > 0.5
Round-Up
Truncate
Round-Up
Truncate
The output of the rounder is latched into the HDF output
register with CK_DEC. CK_DEC is generated by the Clock
Divider section. The output of the register is cleared when
RESET is asserted.
Clock Divider and Control Logic
The clock divider divides CK_IN by the decimation factor
HDEC to produce CK_DEC. CK_DEC clocks the Decimation
Register, Comb Filter section, HDF output register. In the
FIR filter CK_DEC is used to indicate that a new data sample
is available for processing. The clock generator is cleared by
RESET and is not enabled until the DDF is started by an
internal start signal (see “Start Logic” on page 9).
The Control Register Logic enables the updating of the Control
registers which contain all of the filter parameter data. When
WR and CS are asserted, the control register addressed by bits
A0 and A1 is loaded with the data on the C_BUS.
Rounder
The filter accuracy is limited by the 16-bit data input. To
maintain the maximum accuracy, the output of the comb is
rounded to 16 bits.
The Rounder performs a symmetric round of the 19-bit
output of the last Comb stage. Symmetric rounding is done
to prevent the synthesis of a 0Hz spectral component by the
rounding process and thus causing a reduction in spurious
free dynamic range. Saturation logic is also provided to
prevent roll over from the largest positive value to the most
negative value after rounding. The output of the last comb
FN2486 Rev 10.00
Oct 10, 2008
Page 5 of 21
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