MC100LVEP210MNG データシートの表示（PDF） - ON Semiconductor
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MC100LVEP210MNG Datasheet PDF : 9 Pages
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MC100LVEP210
VCC Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 VCC
Exposed Pad
(EP)
VCC Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 VCC
32 31 30 29 28 27 26 25
VCC
Qa3 VCC 1
24 Qa3
NC
Qa3 NC 2
23 Qa3
CLKa
Qa4 CLKa 3
22 Qa4
CLKa
VBB
CLKb
CLKb
VEE
MC100LVEP210
Qa4 CLKa 4
Qb0 VBB 5
Qb0 CLKb 6
Qb1 CLKb 7
Qb1 VEE 8
MC100LVEP210
21 Qa4
20 Qb0
19 Qb0
18 Qb1
17 Qb1
VCC Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 VCC
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. 32−Lead QFN Pinout (Top View)
9 10 11 12 13 14 15 16
VCC Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 VCC
Figure 2. LQFP−32 Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
CLKn*, CLKn**
ECL/PECL/HSTL CLK Inputs
FUNCTION
Qn0:4, Qn0:4
ECL/PECL Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
EP
The exposed pad (EP) on the QFN−32 package bottom is thermally connected to the die for im-
proved heat transfer out of the package. THe exposed pad must be attached to a heat−sinking
conduit. The pad is electrically connected to VEE.
* Pins will default LOW when left open.
** Pins will default to VCC/2 when left open.
CLKa
CLKa
Qa0
Qb0
Qa0
Qb0
Qa1
Qb1
CLKb
Qa1
Qb1
Qa2
CLKb
Qb2
Qa2
Qb2
Qa3
Qb3
VBB
Qa3
Qb3
Qa4
VCC
Qa4
VEE
Qb4
Qb4
Figure 3. Logic Diagram
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