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CAT811JTBI-T3 データシートの表示(PDF) - Catalyst Semiconductor => Onsemi

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CAT811JTBI-T3
Catalyst
Catalyst Semiconductor => Onsemi Catalyst
CAT811JTBI-T3 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
CAT811, CAT812
PIN DESCRIPTION
Pin Number
CAT811 CAT812
1
1
Name
GND
2
R¯¯E¯S¯E¯T¯
2
RESET
3
3
¯M¯R¯
4
4
VCC
Description
Ground
Active LOW reset. R¯¯E¯S¯E¯T¯ is asserted if VCC falls below the reset threshold
and remains low for at least 140ms after VCC rises above the reset threshold.
Active HIGH reset. RESET is asserted if VCC falls below the reset threshold
and remains high for at least 140ms after VCC rises above the reset
threshold.
Manual Reset Input. A logic LOW on ¯M¯R¯ asserts RESET. RESET remains
active as long as ¯M¯R¯ is LOW and for 140ms after ¯M¯R¯ returns HIGH. The
active low input has an internal 20kpull-up resistor. The input should be
left open if not used.
Power supply voltage that is monitored.
BLOCK DIAGRAM
MR
VCC
VCC
TOLERANCE
+
BIAS
RESET
&
DIGITAL
DELAY
VCC
RESET
VOLTAGE
REFERENCE
GND
CAT811
MR
VCC
VCC
TOLERANCE
+
BIAS
RESET
&
DIGITAL
DELAY
VCC
RESET
VOLTAGE
REFERENCE
GND
CAT812
Doc. No. MD-3005 Rev. S
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

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