74LV4060-Q100 データシートの表示（PDF） - Nexperia B.V. All rights reserved
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74LV4060-Q100 Datasheet PDF : 21 Pages
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74LV4060-Q100
14-stage binary ripple counter with oscillator
Rev. 1 — 25 July 2014
Product data sheet
1. General description
The 74LV4060-Q100 is a low-voltage Si-gate CMOS device and is pin and function
compatible with the 74HC4060-Q100; 74HCT4060-Q100.
The 74LV4060-Q100 is a 14-stage ripple-carry counter/divider and oscillator with three
oscillator terminals (RS, RTC and CTC). It has ten buffered outputs (Q3 to Q9 and Q11 to
Q13) and an overriding asynchronous master reset (MR). The oscillator configuration
allows design of either RC or crystal oscillator circuits. The oscillator can be replaced by
an external clock signal at input RS. In this case, keep the oscillator pins (RTC and CTC)
floating.
The counter advances on the negative-going transition of RS. A HIGH-level on MR resets
the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of the other input conditions.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide operating voltage range from 1.0 V to 5.5 V
Optimized for low voltage applications from 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V; Tamb = 25 C
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V; Tamb = 25 C
All active components on chip
RC or crystal oscillator configuration
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
3. Applications
Control counters
Timers
Frequency dividers
Time-delay circuits
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