AD5554BRS(RevA) データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD5554BRS Datasheet PDF : 20 Pages
| |||
AD5544/AD5554
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGNDA 1
IOUTA 2
VREFA 3
RFBA 4
28 AGNDD
27 IOUTD
26 VREFD
25 RFBD
MSB 5 AD5544/ 24 DGND
RS 6 AD5554 23 VSS
VDD 7 TOP VIEW 22 AGNDF
CS 8 (Not to Scale) 21 LDAC
CLK 9
20 SDO
SDI 10
19 NC
RFBB 11
VREFB 12
IOUTB 13
AGNDB 14
18 RFBC
17 VREFC
16 IOUTC
15 AGNDC
NC = NO CONNECT
Table 4. Pin Function Descriptions
Figure 3. AD5544/AD5554 Pin Configuration
Pin
No. Name
Function
1
AGNDA
DAC A Analog Ground.
2
IOUTA
DAC A Current Output.
3
VREFA
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.
4
RFBA
Establish voltage output for DAC A by connecting to external amplifier output.
5
MSB
MSB Bit. Set pin during a reset pulse (RS) or at system power ON if tied to ground or VDD.
6
RS
7
VDD
8
CS
Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for AD5544
and 2000H for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB = 0.
Register Data = 8000H for AD5544 and 2000H.
Positive Power Supply Input. Specified range of operation 5 V ±10%.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input
register when CS/LDAC returns high. Does not effect LDAC operation.
9
CLK
Clock Input. Positive edge clocks data into shift register.
10 SDI
Serial Data Input. Input data loads directly into the shift register.
11
RFBB
Establish voltage output for DAC B by connecting to external amplifier output.
12
VREFB
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.
13
IOUTB
DAC B Current Output.
14
AGNDB
DAC B Analog Ground.
15
AGNDC
DAC C Analog Ground.
16
IOUTC
DAC C Current Output.
17
VREFC
18
RFBC
19 NC
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.
Establish voltage output for DAC C by connecting to external amplifier output.
No Connect. Leave pin unconnected.
20 SDO
Serial Data Output. Input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for AD5544
and 17 clock pulses for AD5554 after input at the SDI pin.
21
LDAC
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous
active low input. See Table 5 and Table 6 for operation.
22 AGNDF High Current Analog Force Ground.
23 VSS
Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.
24 DGND Digital Ground Pin.
25
RFBD
Establish Voltage Output for DAC D by Connecting to External Amplifier Output.
26
VREFD
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.
27
IOUTD
DAC D Current Output.
28
AGNDD
DAC D Analog Ground.
Rev. A | Page 7 of 20
Share Link: 