ADP3026ARU データシートの表示（PDF） - Analog Devices

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ADP3026ARU

High-Efficiency Notebook Computer Power Supply Controller

Analog Devices 

ADP3026

PRELIMINARY TECHNICAL DATA

THEORY OF OPERATION

The ADP3026 is a dual-mode, step-down power supply con-

troller for notebook computers or similar battery-powered

applications. The device contains two synchronous step-

down buck controllers and a linear regulator controller. The

buck controllers in the ADP3026 have the ability to pro-

vide fixed 3.3 V and 5 V outputs. High efficiency over a

broad load range is achieved by using a proprietary dual-mode

PWM/power-saving (PSV) mode architecture. Efficiency is

further improved by deleting the external current sense resistor,

which is the main contributor to loss during high current, low

output voltage conditions.

CIRCUIT DESCRIPTION

Dual-Mode Architecture

The ADP3026 contains two independent dual-mode, syn-

chronous buck controllers. Traditional constant frequency

PWM buck converters suffer from relatively low efficiency

under light load conditions. In order to maintain high effi-

ciency over a wide load range, the ADP3026 use a proprietary

dual-mode architecture. At moderate to heavy loads, the buck

converter operates in the traditional Pulsewidth Modulation

(PWM) mode. At light loads, PSV mode is used to increase

system efficiency. A proprietary detection scheme is used for

transition from one mode to the other. Input current to the

high-side MOSFET is detected when going from PWM

mode to PSV mode, and output voltage information is used

when changing from PSV mode to PWM mode.

When the high-side N-channel MOSFET is turned on, the

current going through the N-channel MOSFET is measured as

a voltage between CS and SW. If the peak current through

the MOSFET is less than 20% of the current limit value

set by CLSET, an internal counter that is based on the os-

cillator frequency will be started. If the current stays below

this threshold for 16 PWM cycles, the buck converter will

enter power-saving mode. The counter will automatically

reset if the peak current is higher than 20% of the current

limit value any time prior to when the counter reaches 16.

In PSV mode, the buck converter works like a window regu-

lator. If the output voltage drops below the PWM mode

nominal output voltage, the high-side MOSFET will be

turned on. It will remain on until the output capacitors are

charged up to 2% above the PWM mode nominal output

voltage. The high-side MOSFET will then be latched off until

the output capacitors are discharged to the lower threshold.

The discharge rate is dependent on the output capacitor

value and load current.

It is important to note that the current limit threshold when

in PSV mode is approximately 1/4 of the current limit

threshold when in PWM mode. If a large load is applied to

the converter when in PSV mode (for example, larger than

the current limit in PSV mode), the output will continue to

drop due to the lower current limit threshold of PSV mode.

When the output voltage drops to 2% below the PWM mode

nominal voltage, the converter will automatically return to

PWM mode. Once in PWM mode, the current limit is qua-

drupled, and the output will be charged up to the nominal

level, as long as the load does not exceed the higher PWM

current limit.

PWM/PSV Operation

Table I shows the summary of the operating modes of the syn-

chronous buck controllers.

Table I. PWM Mode and PSV Mode

Load

Current

Heavy

Moderate

Light

Operating

Mode

Description

PWM

PWM

PSV

Constant-Frequency PWM

Constant-Frequency PWM

Variable-Frequency, Burst Mode

Internal 5 V Supply (INTVCC)

An internal low dropout regulator (LDO) generates a 5 V sup-

ply (INTVCC) that powers all of the functional blocks

within the IC. The total current rating of this LDO is 50

mA. However, this current is used for supplying gate-drive

power, and it is not recommended that current be drawn

from this pin for other purposes. Bypass INTVCC to

AGND with a 4.7 µF capacitor. A UVLO circuit is also in-

cluded in the regulator. When INTVCC < 3.8 V, the two

switching regulators, and the linear regulator controller

are shut down. The UVLO hysteresis voltage is about 120

mV. The internal LDO has a built-in fold-back current

limit, so that it will be protected if a short circuit is ap-

plied to the 5 V output.

Reference (REF)

The ADP3026 contains a precision 800 mV bandgap refer-

ence. Bypass REF to AGND with a 22 nF ceramic

capacitor. The reference is intended for internal use only.

Boost High-Side Gate Drive Supply (BST)

The gate drive voltage for the high-side N-channel

MOSFET is generated by a flying-capacitor boost circuit. The

boost capacitor connected between BST and SW is charged

from the INTVCC supply. Use only small-signal diodes for

the boost circuit.

Synchronous Rectifier (DRVL)

Synchronous rectification is used to reduce conduction

losses and to ensure proper start-up of the boost gate

driver circuit. Antishoot-through protection has been in-

cluded to prevent cross conduction during switch

transitions. The low-side driver must be turned off before

the high-side driver is turned on. For typical N-channel

MOSFETs, the dead time is about 50 ns. On the other

edge, a dead time of about 50 ns is achieved by an internal

delay circuit. The synchronous rectifier is turned off when

the current flowing through the low-side MOSFET falls to

zero when in Discontinuous Conduction (DCM) PWM mode

and PSV mode. In Continuous Conduction (CCM) PWM

mode, the current flowing through the low-side MOSFET

never reaches zero, so the synchronous rectifier is turned off

by the next clock cycle.

–10–

REV. PrB

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