STK7565A_ データシートの表示（PDF） - SANYO -> Panasonic

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STK7565A_

Chopper Type Parallel 2-Output Voltage Regulators

SANYO -> Panasonic 

STK7560 Series

where Tj max=150°C, Pd : Power dissipation PT1, PF1, PT2, PF2 in each element,

θjc=Junction-case thermal resistance in each element.

Type No.

STK7560A

Table of Thermal Resistance θjc

OUTPUT 1

OUTPUT 2

TR1 D3 TR6 D4

4.9 12.5 4.9 12.5

STK7560F

STK7560G

4.7 12.5 2.7

5.5

STK7560J

2.7

5.5

4.7 12.5

To dessipate heat satisfactorily, use a heat sink with thermal resistance θca meeting two temperature conditions of

Tc max=105°C, Tj max=105°C.

Since the actual thermal resistance of the heat sink

greatly depends on various conditions such as equip-

ment layout or ventilation, allow an ample margin in

thermal design. Shown right is the relation between Al

heat sink area and thermal resistance. The Al surface

coated with black improves thermal characteristic,

lowering thermal resistance approximately 20% as

compared with the Al heat sink of the same area.

Description of Operation of Internal Blocks

[OSC]

External excitation type OSC circuit where the CMOS NAND

gate-used ring OSC is formed by the 2-stage NAND circuit,

delivering basic pulses. This circuit provides pulse width modula-

tion where the frequency is constant and the duty only varies.

[PWM]

Pulse width modulation (PWM) is provided by differentiating the

output of NAND gate 2 using the differentiating circuit of time

constant CR as shown left and by applying the result to the input of

NAND gate 3.

The threshold voltage at the input of NAND gate 3 is approxi-

mately 1/2 of supply voltage VDD applied to the gate and the PWM

output as shown below is obtained.

No.1773–11/13

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