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STK7562J_ データシートの表示(PDF) - SANYO -> Panasonic

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STK7562J_ Datasheet PDF : 13 Pages
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STK7560 Series
‘High active’ setting of cutoff input
‘Low active’ setting of cutoff input can be changed to ‘High active’ setting as shown below.
Sample Printed Circuit Pattern
Standard peripheral circuit for Sample Application Circuit 1 (Cu-foiled area)
Precautions
· Make the large current-carrying lines thicker and shorter.
· Please high input capacitor C1 close to the input pin of the
IC.
· Place switching spike-reducing C6, C7 close to the IC pins.
· Connect GND of ferrite bead core to GND of input capaci-
tor C1 to minimize the core, C1-related pattern loop area.
· Connect V SENSE GND (pin 12) to GND of current line
near the load.
· Connect GND of output capacitors C3, C4, C5, C8 near the
load not to oppose current flow.
· Connect pins connected inside the IC (pins 6, 7, etc.) also on
the printed circuit board.
· Do not use NC (pin 18) as a relay pin for otherline, pin.
Resons
To minimize voltage loss on the pattern
To minimize input ripple.
To reduce switching spike more effectively.
To reduce switching spike more effectively.
To improve load regulation characteristic of
output voltage.
To improve ripple characteristic.
To provent current from concentrating on pin.
No.1773–6/13

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