EVAL-ADN2811-CML データシートの表示（PDF） - Analog Devices
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EVAL-ADN2811-CML Datasheet PDF : 20 Pages
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ADN2811
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
PIN 1
INDICATOR
THRADJ 1
VCC 2
VEE 3
VREF 4
PIN 5
NIN 6
SLICEP 7
SLICEN 8
VEE 9
LOL 10
XO1 11
XO2 12
ADN2811
TOP VIEW
(Not to Scale)
36 VCC
35 VCC
34 VEE
33 VEE
32 NC
31 NC
30 RATE
29 VEE
28 VCC
27 VEE
26 VCC
25 CF2
Data Sheet
NOTES
1. EXPOSED PAD IS TIED OFF TO VCC PLANE WITH VIAS.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Type1
1
THRADJ
AI
2, 26, 28
VCC
P
3, 9, 16, 19, 22, 27, VEE
P
29, 33, 34, 42, 43, 46
4
VREF
AO
5
PIN
AI
6
NIN
AI
7
SLICEP
AI
8
SLICEN
AI
10
LOL
DO
11
XO1
AO
12
XO2
AO
13
REFCLKN DI
14
REFCLKP DI
15
REFSEL
DI
17
TDINP
AI
18
TDINN
AI
20, 47
VCC
P
21
CF1
AO
23
REFSEL1
DI
24
REFSEL0
DI
25
CF2
AO
30
RATE
DI
31, 32
NC
DI
35, 36
VCC
P
37
DATAOUTN DO
38
DATAOUTP DO
39
SQUELCH DI
40
CLKOUTN DO
41
CLKOUTP DO
44
BYPASS
DI
45
SDOUT
DO
48
LOOPEN
DI
Not applicable
EPAD
FP
Description
LOS Threshold Setting Resistor.
Analog Supply.
Ground.
Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
Loss of Lock Indicator. LVTTL active high.
Crystal Oscillator.
Crystal Oscillator.
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
Reference Source Select. 0 = on-chip oscillator with external crystal; 1 = external clock source, LVTTL.
Differential Test Data Input.
Differential Test Data Input.
Digital Supply.
Frequency Loop Capacitor.
Reference Frequency Select (See Table 5) LVTTL.
Reference Frequency Select (See Table 5) LVTTL.
Frequency Loop Capacitor.
Data Rate Select (See Table 4) LVTTL.
No Connect.
Output Driver Supply.
Differential Retimed Data Output. CML.
Differential Retimed Data Output. CML.
Disable Clock and Data Outputs. Active high. LVTTL.
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Bypass CDR Mode. Active high. LVTTL.
Loss of Signal Detect Output. Active high. LVTTL.
Enable Test Data Inputs. Active high. LVTTL.
Exposed Pad. Exposed pad is tied off to VCC plane with vias.
1 Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output, FP = floating pad.
Rev. C | Page 6 of 20
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