ADM1064ACP データシートの表示（PDF） - Analog Devices

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ADM1064ACP

Super Sequencer™ with Voltage Readback ADC

Analog Devices 

ADM1064

Parameter

SERIAL BUS TIMING

Clock Frequency, fSCLK

Bus Free Time, tBUF

Start Setup Time, tSU;STA

Start Hold Time, tHD;STA

SCL Low Time, tLOW

SCL High Time, tHIGH

SCL, SDA Rise Time, tr

SCL, SDA Fall Time, tf

Data Setup Time, tSU;DAT

Data Hold Time, tHD;DAT

Input Low Current, IIL

SEQUENCING ENGINE TIMING

State Change Time

Min

Typ Max Unit Test Conditions/Comments

400 kHz

4.7

µs

4.7

µs

4

µs

4.7

µs

4

µs

1000 µs

300 µs

250

ns

5

ns

1

µA

VIN = 0

10

µs

1 At least one of the VH, VP1-4 pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.

2 Specification is not production tested, but is supported by characterization data at initial product release.

Rev. 0 | Page 6 of 32

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