EVAL-ADG2188EBZ データシートの表示（PDF） - Analog Devices

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EVAL-ADG2188EBZ

I2C® CMOS 8 × 8 Unbuffered Analog Switch Array with Dual/Single Supplies

Analog Devices 

ADG2188

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Data Sheet

VSS 1

DNC 2

X0 3

X1 4

X2 5

X3 6

X4 7

X5 8

ADG2188

TOP VIEW

(Not to Scale)

24 VDD

23 DNC

22 DNC

21 DNC

20 DNC

19 DNC

18 X7

17 X6

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PADDLE IS SOLDERED TO VSS.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions1

Pin No. Mnemonic Description

1

VSS

Negative Power Supply in a Dual-Supply Application. For single-supply applications, this pin must be tied to GND.

2, 19 to 23 DNC

Do No Connect.

3 to 8,

17, 18

X0 to X7 Can be inputs or outputs.

9 to 16

Y0 to Y7 Can be inputs or outputs.

24

VDD

Positive Power Supply Input.

25

VL

Logic Power Supply Input.

26

SDA

Digital I/O. Bidirectional open drain data line. External pull-up resistor required.

27

SCL

Digital Input, Serial Clock Line. Open drain input that is used in conjunction with SDA to clock data into the

device. External pull-up resistor required.

28

A0

Logic Input. Address pin that sets the least significant bit of the 7-bit slave address.

29

A1

Logic Input. Address pin that sets the second least significant bit of the 7-bit slave address.

30

A2

Logic Input. Address pin that sets the third least significant bit of the 7-bit slave address.

31

RESET

Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are cleared to 0.

32

GND

Ground. Reference point for all circuitry on the ADG2188.

EPAD

Exposed Paddle. The exposed paddle is soldered to VSS.

1 It is recommended that the exposed paddle be soldered to VSS to improve heat dissipation and crosstalk.

Rev. B | Page 10 of 28

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