EVAL-ADG2188EBZ データシートの表示（PDF） - Analog Devices

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EVAL-ADG2188EBZ

I2C® CMOS 8 × 8 Unbuffered Analog Switch Array with Dual/Single Supplies

Analog Devices 

Data Sheet

ADG2188

I2C TIMING SPECIFICATIONS

VDD = 5 V to 12 V; VSS = −5 V to 0 V; VL = 5 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted (see Figure 2).

Table 3.

Parameter1

fSCL

t1

t2

t3

t4 3

t5

t6

t7

t8

t9

t10

Test Conditions/Comments

Standard mode

Fast mode

High speed mode2

CB = 100 pF maximum

CB = 400 pF maximum

Standard mode

Fast mode

High speed mode2

CB = 100 pF maximum

CB = 400 pF maximum

Standard mode

Fast mode

High speed mode2

CB = 100 pF maximum

CB = 400 pF maximum

Standard mode

Fast mode

High speed mode2

Standard mode

Fast mode

High speed mode2

CB = 100 pF maximum

CB = 400 pF maximum

Standard mode

Fast mode

High speed mode2

Standard mode

Fast mode

High speed mode2

Standard mode

Fast mode

Standard mode

Fast mode

High speed mode2

Standard mode

Fast mode

High speed mode2

CB = 100 pF maximum

CB = 400 pF maximum

Standard mode

Fast mode

High speed mode2

CB = 100 pF maximum

CB = 400 pF maximum

ADG2188 Limit at TMIN, TMAX

Min

Max Unit

100 kHz

400 kHz

3.4 MHz

1.7 MHz

4

µs

0.6

µs

60

ns

120

ns

4.7

µs

1.3

µs

160

ns

320

ns

250

ns

100

ns

10

ns

0

3.45 µs

0

0.9 µs

0

0

4.7

0.6

160

4

0.6

160

4.7

1.3

4

0.6

160

20 + 0.1 CB

70

ns

150 ns

µs

µs

ns

µs

µs

ns

µs

µs

µs

µs

ns

1000 ns

300 ns

10

80

ns

20

160 ns

300 ns

20 + 0.1 CB 300 ns

10

80

ns

20

160 ns

Description

Serial clock frequency

tHIGH, SCL high time

tLOW, SCL low time

tSU;DAT, data setup time

tHD;DAT, data hold time

tSU;STA, setup time for a repeated start condition

tHD;STA, hold time for a (repeated) start condition

tBUF, bus free time between a stop and a start condition

tSU;STO, setup time for a stop condition

tRDA, rise time of SDA signal

tFDA, fall time of SDA signal

Rev. B | Page 7 of 28

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