D2-45057 データシートの表示（PDF） - Renesas Electronics
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D2-45057 Datasheet PDF : 30 Pages
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D2-45057, D2-45157
Pin Description (Continued)
PIN
NAME
PIN (Note 13) TYPE
4
SCL
I/O
5
SCLK
I
6
SDIN
I
7
LRCK
I
8
MCLK
O
9
CVDD
P
10 CGND GND
11 RGND GND
12 RVDD
P
13 TEMPREF/ I/O
SCK
14 nMUTE/
O
TIO1
15 VOL1/
I/O
MISO
16 TEMP1/ I/O
MOSI
17 SPDIFRX
I
18 SPDIFTX O
19
TEST
I
20
IRQA
I
21
IRQB
I
22 RGND GND
23 RVDD
P
24 nERROR/ I/O
CFG0
VOLTAGE
LEVEL
(V)
DESCRIPTION
3.3
Two-Wire Serial clock port, open drain driver with 8mA drive strength. Bidirectional signal is used by both the
master and slave controllers for clock signaling. Pin floats on reset.
3.3
I2S Serial Audio Bit Clock (SCLK) Input. Input has hysteresis.
3.3
I2S Serial Audio Data (SDIN) Input. Input has hysteresis.
3.3
I2S Serial Audio Left/Right (LRCK) Input. Input has hysteresis.
3.3
I2S Serial Audio Master Clock output for external ADC/DAC components, drives low on reset. Output is an
8mA driver.
3.3
Core power, +1.8VDC. Used in the chip internal DSP, logic and interfaces.
3.3
Core ground.
3.3
Digital pad ring ground. Internally connected to PWMGND.
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and receivers, except
for the analog pads. There are 2 of these pins and both are required to be connected. Internally connected to
PWMVDD.
3.3
Reference pin for temperature monitor and SPI clock. At deassertion of device reset, pin operates as SPI
clock with 8mA drive strength. Upon internal D2-45057, D2-45157 firmware execution, pin becomes
temperature monitor reference.
3.3
Mute signal output. Low active: mute condition drives pin low. Output is a 16mA driver. Initializes as input on
reset, then becomes output upon internal firmware execution.
3.3
Volume control pulse input and SPI master- input/slave-output data signal. At deassertion of device reset,
pin operates as SPI master input or slave output. (When operating as output, provides 4mA drive strength.)
Then upon internal D2-45057, D2-45157 firmware execution, pin becomes input for monitoring up/down
phase pulses from volume control. (1 of 2 volume input pins.)
3.3
Board temperature monitor pin, and SPI master-output/slave-input data signal. At deassertion of device
reset, pin operates as SPI master output or slave input. (When operating as output, provides 4mA drive
strength.) Then upon internal D2-45057, D2-45157 firmware execution, pin becomes input for monitoring
board temperature.
3.3
S/PDIF Digital audio data input
3.3
S/PDIF Digital audio data output This pin is the S/PDIF audio output and drives a 8mA, 3.3V stereo output
up to 192kHz. Pin floats on reset.
3.3
Hardware test mode control. For factory use only. Must be tied low.
3.3
Interrupt request port A. One of 2 IRQ pins, tied to logic (3.3V) high or to ground. High/low logic status
establishes boot mode selection upon deassertion of reset (nRESET) cycle.
3.3
Interrupt request port B. One of 2 IRQ pins, tied to logic (3.3V) high or to ground. High/low logic status
establishes boot mode selection upon deassertion of reset (nRESET) cycle.
3.3
Digital pad ring ground. Internally connected to PWMGND.
3.3
Digital pad ring power, 3.3V. This 3.3V supply is used for all the digital I/O pad drivers and receivers, except
for the analog pads. There are 2 of these pins and both are required to be connected. Internally connected to
PWMVDD.
3.3
Output configuration selection input, and nERROR output. Upon device reset, pin operates as input, using
application-installed pull-up or pull-down connection to pin to specify one of 4 amplifier configurations. Upon
internal D2-45057, D2-45157 firmware execution, pin becomes output, providing active-low output drive
when amplifier protection monitoring detects an error condition. When operating as output, provides 4mA
drive strength. (Note: This pin may also be referenced as “PSCURR” on some reference designs. Function is
identical regardless of name.)
FN6785 Rev 1.00
May 5, 2016
Page 10 of 30
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