CY62128EV30LL-55ZXE データシートの表示（PDF） - Cypress Semiconductor

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CY62128EV30LL-55ZXE

1 Mbit (128K x 8) Static RAM

Cypress Semiconductor 

CY62128EV30 MoBL®

1 Mbit (128K x 8) Static RAM

Features

■ Very High Speed: 45 ns

■ Temperature Ranges:

❐ Industrial: –40°C to +85°C

❐ Automotive-A: –40°C to +85°C

❐ Automotive-E: –40°C to +125°C

■ Wide Voltage Range: 2.2 V to 3.6 V

■ Pin Compatible with CY62128DV30

■ Ultra Low Standby Power

❐ Typical standby current: 1 μA

❐ Maximum standby current: 4 μA

■ Ultra Low Active Power

❐ Typical active current: 1.3 mA @ f = 1 MHz

■ Easy Memory Expansion with CE1, CE2 and OE Features

■ Automatic Power Down when Deselected

■ CMOS for Optimum Speed and Power

■ Offered in Pb-free 32-pin SOIC, 32-pin TSOP I, and 32-pin

STSOP Packages

Logic Block Diagram

Functional Description

The CY62128EV30[1] is a high performance CMOS static RAM

module organized as 128K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device into standby mode reduces power consumption by more

than 99 percent when deselected (CE1 HIGH or CE2 LOW). The

eight input and output pins (I/O0 through I/O7) are placed in a

high impedance state when the device is deselected (CE1 HIGH

or CE2 LOW), the outputs are disabled (OE HIGH), or a write

operation is in progress (CE1 LOW and CE2 HIGH and WE

LOW).

To write to the device, take Chip Enable (CE1 LOW and CE2

HIGH) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins is then written into the location specified on the Address pin

(A0 through A16).

To read from the device, take Chip Enable (CE1 LOW and CE2

HIGH) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

INPUT BUFFER

IO0

A0

A1

IO1

A2

A3

IO2

A4

A5

128K x 8

IO3

A6

A7

ARRAY

IO4

A8

A9

IO5

A10

A11

IO6

CE1

CE2

WE

COLUMN DECODER

POWER

DOWN

IO7

OE

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court

Document #: 38-05579 Rev. *E

• San Jose, CA 95134-1709 • 408-943-2600

Revised May 05, 2009

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