LTC1426 データシートの表示（PDF） - Linear Technology

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LTC1426

Micropower Dual 6-Bit PWM DAC

Linear Technology 

BLOCK DIAGRAM

LATCH

AND

LOGIC

MODE SELECT

0 = PUSHBUTTON MODE

1 = PULSE MODE

CLK1

CLK2

INPUT

CONDITIONING

CONTROL

LOGIC

DEBOUNCE

CIRCUIT

SHDN

POWER-ON

RESET

6-BIT

6

UP/DOWN

COUNTER

6-BIT

6

UP/DOWN

COUNTER

6-BIT

6

UP

COUNTER

OSCILLATOR

COMPARATOR

COMPARATOR

Figure 1. LTC1426 Block Diagram

LTC1426

VREF

DRIVER

PWM1

DRIVER

PWM2

1426 F01

DEFI ITIO S

LSB: The least significant bit or the ideal duty cycle

difference between two successive codes.

LSB = DCMAX/64

DCMAX = The DAC output maximum duty cycle

Resolution: The resolution is the number of DAC output

states (64) that divide the full-scale output duty cycle

range. The resolution does not necessarily imply linearity.

INL: End point integral nonlinearity is the maximum devia-

tion from a straight line passing through the end points of

the DAC transfer curve. The INL error at a given code is

calculated as follows:

INL = (DCOUT – DCIDEAL)/LSB

DCIDEAL = (Code)(LSB)

DCOUT = the DAC output duty cycle measured at the

given number of clocked in pulses.

DNL: Differential nonlinearity is the difference between the

measured duty cycle change and the ideal 1LSB duty cycle

change between any two adjacent codes. The DNL error

between any two codes is calculated as follows:

DNL = (∆DCOUT – LSB)/LSB

∆DCOUT = The measured duty cycle difference between

two adjacent codes.

Full-Scale Error: Full-scale error is the difference between

the ideal and measured DAC output duty cycles with all bits

set to one (Code = 63). The full-scale error is calculated as

follows:

FSE = (DCOUT – DCIDEAL)/LSB

DCIDEAL = DCMAX

APPLICATIONS INFORMATION

Dual 6-Bit PWM DAC

Figure 1 shows a block diagram of the LTC1426. Each

6-bit PWM DAC is guaranteed monotonic and is digitally

adjustable in 64 equal steps, which corresponds from 0%

to 98.5% duty cycle full scale. At power-up, the counters

reset to 100000B and both DAC outputs assume midscale

duty cycle. The PWM outputs have an output impedance

of less than 100Ω. The DAC outputs swing from 0V to the

reference voltage, VREF, which can be biased from 0V to

5.5V. The frequency of the DAC outputs is above 3kHz,

easing output filtering.

In the case of a pure resistive load, the voltage measured

across load RL is given by:

V = (VPWM)RL/(RL + ROUT)

5

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