MPC9772 データシートの表示（PDF） - Integrated Device Technology

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MPC9772

3.3V 1:12 LVCMOS PLL Clock Generator

Integrated Device Technology 

MPC9772 Data Sheet

3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

Table 2. Function Table (Configuration Controls)

Control Default

0

1

REF_SEL

1 Selects CCLKx as the PLL reference clock

Selects the crystal oscillator as the PLL

reference clock

CCLK_SEL 1 Selects CCLK0

Selects CCLK1

VCO_SEL

1 Selects VCO2. The VCO frequency is scaled by a factor of 2 (low VCO Selects VCO1. (high VCO frequency range)

frequency range).

PLL_EN

1 Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL enabled.

internal VCO output. MPC9772 is fully static and no minimum frequency

limit applies. All PLL related AC characteristics are not applicable.

INV_CLK

1 QC2 and QC3 are in phase with QC0 and QC1

QC2 and QC3 are inverted (180 phase shift)

with respect to QC0 and QC1

MR/OE

1 Outputs disabled (high-impedance state) and device is reset. During Outputs enabled (active)

reset/output disable the PLL feedback loop is open and the internal VCO

is tied to its lowest frequency. The MPC9772 requires reset after any loss

of PLL lock. Loss of PLL lock may occur when the external feedback path

is interrupted. The length of the reset pulse should be greater than one

reference clock cycle (CCLKx). The device is reset by the internal power-

on reset (POR) circuitry during power-up.

VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency

ratios. See Table 3 to Table 6 and the Applications Information for supported frequency ranges and output to input frequency ratios.

Table 3. Output Divider Bank A (NA)

VCO_SEL

0

0

0

0

1

1

1

1

FSEL_A1

0

0

1

1

0

0

1

1

FSEL_A0

0

1

0

1

0

1

0

1

QA[0:3]

VCO8

VCO12

VCO16

VCO24

VCO4

VCO6

VCO8

VCO12

Table 4. Output Divider Bank B (NB)

VCO_SEL

0

0

0

0

1

1

1

1

FSEL_B1

0

0

1

1

0

0

1

1

FSEL_B0

0

1

0

1

0

1

0

1

QB[0:3]

VCO8

VCO12

VCO16

VCO20

VCO4

VCO6

VCO8

VCO10

Table 5. Output Divider Bank C (NC)

VCO_SEL

0

0

0

0

1

FSEL_C1

0

0

1

1

0

FSEL_C0

0

1

0

1

0

QC[0:3]

VCO4

VCO8

VCO12

VCO16

VCO2

MPC9772 REVISION 7 JANUARY 8, 2013

4

©2013 Integrated Device Technology, Inc.

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