MPC9772 データシートの表示（PDF） - Integrated Device Technology

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MPC9772

3.3V 1:12 LVCMOS PLL Clock Generator

Integrated Device Technology 

MPC9772 Data Sheet

3.3V 1:12 LVCMOS PLL CLOCK GENERATOR

Table 5. Output Divider Bank C (NC)

VCO_SEL

1

1

1

FSEL_C1

0

1

1

Table 6. Output Divider PLL Feedback (M)

VCO_SEL

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

FSEL_FB2

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

Table 7. General Specifications

Symbol

Characteristics

VTT Output Termination Voltage

MM ESD Protection (Machine Model)

HBM ESD Protection (Human Body Model)

LU Latch-Up Immunity

CPD Power Dissipation Capacitance

CIN

Input Capacitance

FSEL_FB1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

Min

200

2000

200

FSEL_C0

1

0

1

FSEL_FB0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Typ

VCC  2

Max

12

4.0

QC[0:3]

VCO4

VCO6

VCO8

QFB

VCO8

VCO12

VCO16

VCO20

VCO16

VCO24

VCO32

VCO40

VCO4

VCO6

VCO8

VCO10

VCO8

VCO12

VCO16

VCO20

Unit

Condition

V

V

V

mA

pF Per output

pF Inputs

Table 8. Absolute Maximum Ratings(1)

Symbol

Characteristics

Min

Max

Unit

Condition

VCC Supply Voltage

–0.3

3.9

V

VIN DC Input Voltage

–0.3

VCC+0.3

V

VOUT DC Output Voltage

–0.3

VCC+0.3

V

IIN

DC Input Current

20

mA

IOUT DC Output Current

50

mA

TS

Storage Temperature

–65

125

C

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated

conditions is not implied.

MPC9772 REVISION 7 JANUARY 8, 2013

5

©2013 Integrated Device Technology, Inc.

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