PM7385 データシートの表示（PDF） - PMC-Sierra

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PM7385

FRAME ENGINE AND DATALINK MANAGER 84A672

PMC-Sierra 

DATA SHEET

PMC-1990114

ISSUE 6

PM7385 FREEDM-84A672

84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER

WITH ANY-PHY PACKET INTERFACE

1 FEATURES

· Single-chip multi-channel HDLC controller with a 50 MHz, 16 bit “Any-PHY”

Packet Interface (APPI) for transfer of packet data using an external

controller.

· Supports up to 672 bi-directional HDLC channels assigned to a maximum of

84 channelised or unchannelised links conveyed via a Scaleable Bandwidth

Interconnect (SBI) interface.

· Data on the SBI interface is divided into 3 Synchronous Payload Envelopes

(SPEs). Each SPE can be configured independently to carry data for either

28 T1/J1 links, 21 E1 links, or 1 unchannelised DS-3 link.

· Links in an SPE can be configured individually to operate in clear channel

mode, in which case, all framing bit locations are assumed to be carrying

HDLC data.

· Links in an SPE can be configured individually to operate in channelised

mode, in which case, the number of time-slots assigned to an HDLC channel

is programmable from 1 to 24 (for T1/J1 links) and from 1 to 31 (for E1 links).

· Supports three bi-directional HDLC channels each assigned to an

unchannelised link with arbitrary rate link of up to 51.84 MHz when SYSCLK

is running at 45 MHz. Each link may be configured individually to replace one

of the SPEs conveyed on the SBI interface.

· For each channel, the HDLC receiver supports programmable flag sequence

detection, bit de-stuffing and frame check sequence validation. The receiver

supports the validation of both CRC-CCITT and CRC-32 frame check

sequences.

· For each channel, the receiver checks for packet abort sequences, octet

aligned packet length and for minimum and maximum packet length. The

receiver supports filtering of packets that are larger than a user specified

maximum value.

· Alternatively, for each channel, the receiver supports a transparent mode

where each octet is transferred transparently on the receive APPI. For

channelised links, the octets are aligned with the receive time-slots.

· For each channel, time-slots are selectable to be in 56 kbits/s format or 64

kbits/s clear channel format.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 1

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