LTC1727I(Old_V) データシートの表示（PDF） - Linear Technology

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LTC1727I
(Rev.:Old_V)

Micropower Precision Triple Supply Monitors in 8-Lead MSOP and 5-Lead SOT-23 Packages

Linear Technology 

LTC1727/LTC1728

APPLICATIO S I FOR ATIO

Supply Monitoring

The LTC1727 is a low power, high accuracy triple supply

monitoring circuit with three monitor outputs and a

200ms microprocessor reset output.

The LTC1728 is a low power, high accuracy triple supply

monitoring circuit with a single 200ms microprocessor

reset output.

All three VCC inputs must be above predetermined thresh-

olds for reset not to be invoked. The LTC1727/LTC1728

will assert reset during power-up, power-down and brown-

out conditions on any one or all of the VCC inputs.

Power Detect

The LTC1727/LTC1728 are powered from the 3.3V/3V

input pin (VCC3), the 1.8V input pin (VCC18), the 2.5V

input pin (VCC25) or the 5V input pin (VCC5), whichever

pin has the highest potential. This ensures the part pulls

the RST pin low as soon as either input pin is ≥ 1V.

Power-Up

Upon power-up, either the VCC5/VCC25/ VCC18 or VCC3 pin,

can power the part. This ensures that RST will be low when

either VCC5/VCC25/VCC18 or VCC3 reaches 1V. As long as

any one of the VCC inputs is below its predetermined

threshold, RST will stay a logic low. Once all of the VCC

inputs rise above their thresholds, an internal timer is

started and RST is released after 200ms.

RST is reasserted whenever any one of the VCC inputs

drops below its predetermined threshold and remains

asserted until 200ms after all of the VCC inputs are above

their thresholds.

On the LTC1727, each of the comparator outputs will be

low until the VCC input that is monitored by that compara-

tor rises above the appropriate predetermined threshold.

The COMP3, and COMP5/COMP25 outputs are guaran-

teed to be in the correct logic state for either VCC3 or

VCC5/VCC25 greater than 1V. The COMPA output requires

the internal bandgap reference to be valid before the

correct logic state can be output. Therefore, the COMPA

output will be held low until VCCA is above 1V and VCC3 or

VCC5/VCC25 is greater than 2V (typ).

Power-Down

On power-down, once any of the VCC inputs drop below

its threshold, RST is held at a logic low. A logic low of 0.3V

is guaranteed until both VCC3 and VCC5/VCC25/VCC18 drop

below 1V.

Glitch Immunity

The RST output of the LTC1727/LTC1728 have two forms

of glitch immunity built in. First, the input monitors require

the input voltage to transition at least 10% of the input

threshold (0.1 • VRTH) below the input threshold for

approximately 50µs in order to force the monitor output

low. The duration of the transition must be longer for

voltage transitions of lesser magnitude (see Figure 1).

Secondly, the reset pulse width of approximately 200ms

acts to debounce the RST output ensuring that the RST

output will always be in the correct state.

The individual monitor outputs of the LTC1727 do not

have hysteresis and will track the monitor inputs relative

to the monitor’s input threshold (VRTA, VRT25, VRT3 and

VRT5). A very slow moving input voltage with ripple riding

on it may cause the individual monitor outputs (COMPA,

COMP25, COMP3 and COMP5) to toggle on the ripple as

the input voltage passes the input threshold. The slow

response time of the LTC1727’s input monitors has a

tendency to integrate signals on the inputs improving their

immunity to noise and ripple.

450

400

350

300

250

200

150

100

50

0

0.1

1

10

100

RESET MONITOR OVERDRIVE VOLTAGE (% OF VCC)

1727/28 F01

Figure 1. Transient Duration vs Comparator Overdrive

9

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