74LVC16374ADGG データシートの表示（PDF） - Nexperia B.V. All rights reserved

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74LVC16374ADGG

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Nexperia B.V. All rights reserved 

Nexperia

74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range

74LVC16374ADL

-40 °C to +125 °C

74LVC16374ADGG

74LVCH16374ADGG

-40 °C to +125 °C

Name

SSOP48

TSSOP48

Description

plastic shrink small outline package;

48 leads; body width 7.5 mm

plastic thin shrink small outline package;

48 leads; body width 6.1 mm

Version

SOT370-1

SOT362-1

4. Functional diagram

1

24

1OE 2OE

47 1D0

1Q0 2

46 1D1

1Q1 3

44 1D2

1Q2 5

43 1D3

1Q3 6

41 1D4

1Q4 8

40 1D5

1Q5 9

38 1D6

1Q6 11

37 1D7

1Q7 12

36 2D0

2Q0 13

35 2D1

2Q1 14

33 2D2

2Q2 16

32 2D3

2Q3 17

30 2D4

2Q4 19

29 2D5

2Q5 20

27 2D6

2Q6 22

26 2D7

2Q7 23

1CP 2CP

48

Fig. 1. Logic symbol

25 001aaa253

1OE 1 EN1

1CP 48

C3

2OE 24 EN2

2CP 25

C4

1D0 47 3D

1D1 46

1D2 44

1D3 43

1D4 41

1D5 40

1D6 38

1D7 37

2D0 36 4D

2D1 35

2D2 33

2D3 32

2D4 30

2D5 29

2D6 27

2D7 26

1

2 1Q0

3 1Q1

5 1Q2

6 1Q3

8 1Q4

9 1Q5

11 1Q6

12 1Q7

2

13 2Q0

14 2Q1

16 2Q2

17 2Q3

19 2Q4

20 2Q5

22 2Q6

23 2Q7

001aaa254

Fig. 2. IEC logic symbol

1D0

1CP

1OE

DQ

CP

FF1

1Q0

2D0

2CP

2OE

DQ

2Q0

CP

FF2

Fig. 3. Logic diagram

to 7 other channels

to 7 other channels

001aaa255

74LVC_LVCH16374A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 12 — 20 November 2018

© Nexperia B.V. 2018. All rights reserved

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