MPC8349E データシートの表示（PDF） - Freescale Semiconductor

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MPC8349E

PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

RESET Initialization

Table 9. RESET Initialization Timing Specifications (continued)

Parameter/Condition

Min

Max

Unit

Notes

Input hold time for POR configuration signals with respect to

0

—

ns

negation of HRESET

Time for the MPC8349E to turn off POR configuration signals

—

4

with respect to the assertion of HRESET

ns

3

Time for the MPC8349E to turn on POR configuration signals

1

with respect to the negation of HRESET

—

tPCI_SYNC_IN

1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied

to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349E

PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual.

2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349E

PowerQUICC™ II Pro Integrated Host Processor Family Reference Manual.

3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 10 lists the PLL and DLL lock times.

Table 10. PLL and DLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs

DLL lock times

7680

122,880

csb_clk cycles 1, 2

Notes:

1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio

results in the minimum and an 8:1 ratio results in the maximum.

2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

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Freescale Semiconductor

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