MPC8349E データシートの表示（PDF） - Freescale Semiconductor

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MPC8349E

PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

DDR SDRAM

Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)

At recommended operating conditions with GVDD of 2.5 V ± 5%.

Parameter

Symbol1

Min

Max

Unit Notes

MCS(n) output hold with respect to MCK

tDDKHCX

333 MHz

2.0

266 MHz

2.65

200 MHz

3.8

—

ns

4

MCK to MDQS

333 MHz

266 MHz

200 MHz

tDDKHMH

–0.9

–1.1

–1.2

ns

5

0.3

0.5

0.6

MDQ/MECC/MDM output setup with respect to

MDQS

333 MHz

266 MHz

200 MHz

tDDKHDS,

tDDKLDS

900

900

1200

—

ps

6

MDQ/MECC/MDM output hold with respect to

MDQS

333 MHz

266 MHz

200 MHz

tDDKHDX,

tDDKLDX

900

900

1200

—

ps

6

MDQS preamble start

tDDKHMP –0.25 × tMCK – 0.9 –0.25 × tMCK + 0.3

ns

7

MDQS epilogue end

tDDKLME

-0.9

0.3

ns

7

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the clock control register.

For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the

address/command valid with the rising edge of MCK.

4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the

ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by

1/2 applied cycle.

5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)

from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to the same

delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters

have been set to the same adjustment value. See the MPC8349E PowerQUICC™ II Pro Integrated Host Processor Family

Reference Manual, for a description and understanding of the timing modifications enabled by use of these bits.

6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8349E.

7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8349E. Note that tDDKHMP follows the symbol

conventions described in note 1.

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

17

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