LH5420P-25 データシートの表示（PDF） - Sharp Electronics

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LH5420P-25

256 × 36 × 2 Bidirectional FIFO

Sharp Electronics 

256 × 36 × 2 Bidirectional FIFO

WRITE

PORT A

I/O

READ

FIFO 1

FIFO 2

READ

PORT B

I/O

WRITE

PORT A

CONTROL

PORT B

CONTROL

Figure 2a. Simplified LH5420 Block Diagram

LH5420

5420-36

RS

MBF2

A2A

A1A

A0A

CKA

R/WA

ENA

REQA

ACKA

FF1

AF1

HF1

RT2

EF2

AE2

RESET

LOGIC

COMMAND

PORT AND

REGISTER

PORT A

SYNCH-

RONOUS

CONTROL

LOGIC

OEA

D0A - D35A

PORT A

I/O

PFA

PARITY

CHECKING

BYPASS

MAILBOX

REGISTER

#1

MAILBOX

REGISTER

#2

FIFO #1

MEMORY ARRAY

256 x 36

WRITE

POINTER

READ

POINTER

FIXED AND

PROGRAMMABLE

STATUS FLAGS

FIXED AND

PROGRAMMABLE

STATUS FLAGS

READ

POINTER

WRITE

POINTER

FIFO #2

MEMORY ARRAY

256 x 36

RESOURCE

REGISTERS

COMMAND

PORT AND

REGISTER

PORT B

SYNCH-

RONOUS

CONTROL

LOGIC

PORT B

I/O

PARITY

CHECKING

Figure 2b. Detailed LH5420 Block Diagram

MBF1

A0B

CKB

R/WB

ENB

REQB

ACKB

EF1

AE1

RT1

FF2

AF2

HF2

OEB

D0B - D35B

WS0, WS1

PFB

5420-6

6-211

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