LH5420P-25 データシートの表示（PDF） - Sharp Electronics

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LH5420P-25

256 × 36 × 2 Bidirectional FIFO

Sharp Electronics 

256 × 36 × 2 Bidirectional FIFO

LH5420

AC ELECTRICAL CHARACTERISTICS 1 (VCC = 5 V ± 10%, TA = 0°C to 70°C)

SYMBOL

DECRIPTION

–25

MIN MAX

–30

MIN MAX

–35

UNITS

MIN MAX

fCC

tCC

tCH

tCL

tDS

tDH

tES

tEH

tRWS

tRWH

tRQS

tRQH

tAS

tAH

tA

tACK

tOH

tZX

tXZ

tEF

tFF

tHF

tAE

tAF

tMBF

tPF

tRS

tRSS

tRSH

tRF

tFRL

tFWL

tBS

tBH

tBA

Clock Cycle Frequency

—

40

—

33

— 28.5 MHz

Clock Cycle Time

25

—

30

—

35

—

ns

Clock HIGH Time

10

—

12

—

15

—

ns

Clock LOW Time

10

—

12

—

15

—

ns

Data Setup Time

12

—

13

—

15

—

ns

Data Hold Time

0

—

0

—

0

—

ns

Enable Setup Time

13

—

15

—

15

—

ns

Enable Hold Time

0

—

0

—

0

—

ns

Read/Write Setup Time

13

—

15

—

18

—

ns

Read/Write Hold Time

0

—

0

—

0

—

ns

Request Setup Time

15

—

18

—

21

—

ns

Request Hold Time

Address Setup Time 6

Address Hold Time 6

0

—

0

—

0

—

ns

15

—

18

—

21

—

ns

0

—

0

—

0

—

ns

Data Output Access Time

Acknowledge Access Time 8

—

16

—

20

—

25

ns

—

—

—

20

—

25

ns

Output Hold Time

4

—

4

—

4

—

ns

Output Enable Time, OE LOW to D0 – D35 Low-Z 2

5

—

5

—

5

—

ns

Output Disable Time, OE HIGH to D0 – D35 High-Z 2

—

15

—

20

—

25

ns

Clock to EF Flag Valid (Empty Flag)

—

22

—

25

—

30

ns

Clock to FF Flag Valid (Full Flag)

—

22

—

25

—

30

ns

Clock to HF Flag Valid (Half-Full)

—

22

—

25

—

30

ns

Clock to AE Flag Valid (Almost-Empty)

—

20

—

25

—

30

ns

Clock to AF Flag Valid (Almost-Full)

—

20

—

25

—

30

ns

Clock to MBF Flag Valid (Mailbox Flag)

—

15

—

20

—

25

ns

Data to Parity Flag Valid

Reset/Retransmit Pulse Width 7

Reset/Retransmit Setup Time 3

Reset/Retransmit Hold Time 3

—

17

—

20

—

25

ns

40/25 — 52/30 — 65/35 —

ns

20

—

25

—

30

—

ns

10

—

15

—

20

—

ns

Reset LOW to Flag Valid

First Read Latency 4

First Write Latency 5

—

35

—

40

—

45

ns

25

—

30

—

35

—

ns

25

—

30

—

35

—

ns

Bypass Data Setup

15

—

18

—

21

—

ns

Bypass Data Hold

5

—

5

—

5

—

ns

Bypass Data Access

—

20

—

25

—

30

ns

NOTES:

1. Timing measurements performed at ‘AC Test Condition’ levels.

2. Values are guaranteed by design; not currently production tested.

3. tRSS and/or tRSH need not be met unless a rising edge of CKA occurs while ENA is being asserted, or else a rising edge of CKB occurs while

ENB is being asserted.

4. tFRL is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data.

5. tFWL is the minimum first-read-to-first-write delay, following a full condtion, which is required to assure successful writing of data.

6. tAS, tAH address setup times and hold times need only be satisfied at clock edges which occur while the corresponding enables are being as-

serted.

7. First number used only when CKA or CKB is enabled; tRS = tRSS + tCH + tRSH.

8. The REQ/ACK facility is not available at cycle times less than 30 ns.

6-215

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