LR38269 データシートの表示（PDF） - Sharp Electronics
部品番号
コンポーネント説明
メーカー
LR38269 Datasheet PDF : 20 Pages
| |||
LR38269
ADDRESS NAME BIT
69h APT_HCL 6-0
6Ah APT_VGA 4-0
6Bh APT_VCL 6-0
6Ch CBLK_LV 7
SETUP 6-1
6Dh VARI_Y 4-0
6Eh
SW_CTRL 7-0
6Fh
7-5
TG_SEL1
4-2
70h
7-5
TG_SEL2
4-2
71h ENC_MUTE 7
SYNC_SW 6
SEL_RB 5
OUT_GAIN 4-0
72h SYNC_LEV 7-0
73h BAS_R 7-0
74h BAS_B 7-0
75h
7
MUTE_OUT
6-0
76h TEST
2-0
77h VRI
2
TEST
1
TEST
0
78h KEI_AGC 8
CONTENTS
Horizontal aperture signal coring
Vertical aperture gain
Vertical aperture signal coring
CBLK level selection
0 : 00h
1 : 10h
Set up level
luminance signal position
The following setting is available under both EEPSL = H and digital output mode
WB1 (LSB), WB2, BACK, EEMDS, EEMD1 EEMD2, EEMD3, MIR (MSB)
ADCK phase setting (6 steps per 60˚)
FS phase setting (±2 ns x 3)
FCDS phase setting (±2 ns x 3)
FR phase setting (±2 ns x 3)
Encoder muting
0 : OFF
1 : ON
SYNC adder
0 : ON
1 : OFF
Serial digital data setting
Gain of video output amplifier
SYNC level (80h = 40 IRE)
BURST level of R – Y
BURST level of B – Y
Muting at power-on
Muting period (data multiplied by 1 field period)
Test data (EEPROM data must be 00h)
EXCKI pin function
1 : VRI function 0 : Clock input
Test data (EEPROM data must be 0)
Test data (EEPROM data must be 0)
AGC gain to set KEI-PULSE high
(NOTE 1)
ADDRESS
01
Bit 3
Bit 2
DIGITAL
1
1
0
x
ANALOG
1
0
0
1
0
Bit 0
0
0
1
0
0
1
1
DCK1 (Pin 47)
DCK1
DCK1
DCK1
CSYNC
CSYNC
CSYNC
CSYNC
SIGNAL OUTPUT
VD (Pin 61)
VD for video out
VD for CCD driving
CSYNC
VD for video out
VD for CCD driving
VD for video out
VD for CCD driving
HD (Pin 60)
HD
HD
HD
HD
HD
BELL
BELL
11
Share Link: 