NCP1616 データシートの表示（PDF） - ON Semiconductor

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NCP1616

High Voltage High Efficiency Power Factor Correction Controller

ON Semiconductor 

NCP1616

VCC(off), typically 9.0 V, is reached. Once reached, the PFC

controller is disabled reducing the bias current consumption

of the IC.

The controller is disabled once a fault is detected. The

controller will restart next time VCC reaches VCC(on) or after

all non−latching faults are removed.

The supply capacitor provides power to the controller

during power up. The capacitor must be sized such that a

VCC voltage greater than VCC(off) is maintained while the

auxiliary supply voltage is building up. Otherwise, VCC will

collapse and the controller will turn off. The operating IC

bias current, ICC5, and gate charge load at the drive outputs

must be considered to correctly size CVCC. The increase in

current consumption due to external gate charge is

calculated using Equation 1.

ICC(gatecharge) + f @ QG

(eq. 1)

where f is the operating frequency and QG is the gate charge

of the external MOSFETs.

OPERATING MODE

The NCP1616 PFC controller achieves power factor

correction using the novel Current Controlled Frequency

Foldback (CCFF) topology. In CCFF the circuit operates in

the classical critical conduction mode (CrM) when the

inductor current exceeds a programmable value. Once the

current falls below this preset level, the frequency is linearly

reduced, reaching about 26 kHz when the current is zero.

Figure 3. CCFF Operation

As illustrated in the top waveform in Figure 3, at high

load, the boost stage operates in CrM. As the load decreases,

the controller operates in a controlled frequency

discontinuous mode.

Figure 4 details CCFF operation. A voltage representative

of the input current (“current information”) is generated. If

this signal is higher than a 2.5 V internal reference (named

“Dead−Time Ramp Threshold”), there is no deadtime and

the circuit operates in CrM. If the current information signal

is lower than the 2.5 V threshold, deadtime is added. The

deadtime is the time necessary for the internal ramp to reach

2.5 V from the current information floor. Hence, the lower

the current information is, the longer the deadtime.

To further reduce the losses, the MOSFET turn on is

further delayed until its drain−source voltage is at its valley.

As illustrated in Figure 4, the ramp is synchronized to the

drain−source ringing. If the ramp exceeds the 2.5 V

threshold while the drain−source voltage is below Vin, the

ramp is extended until it oscillates above Vin so that the drive

will turn on at the next valley.

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