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NCV8851-1DBR2G データシートの表示(PDF) - ON Semiconductor

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NCV8851-1DBR2G
ON-Semiconductor
ON Semiconductor ON-Semiconductor
NCV8851-1DBR2G Datasheet PDF : 18 Pages
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NCV8851−1
This sequence begins once VIN_IC surpasses its UVLO
threshold when the part is enabled and the LDO output has
risen. After an initial delay to assure a clean start−up,
switching begins, the output initially rises quickly and then
rises monotonically. The duty cycle is gradually increased
until VOUT has reached its set point or until maximum duty
cycle is reached.
Normal Shutdown Behavior and Sleep Mode
Normal shutdown occurs when the IC stops switching
because the input supply drops below the UVLO threshold,
the part enters TSD or the part is disabled. When disabled,
the part enters sleep mode.
In sleep mode, the LDO turns off and its output capacitor
discharges, causing switching to stop, the internal soft−start
capacitor to discharge and GH and GL to go low. The switch
node enters a high impedance state and the output inductor
and capacitors discharge through the load. The supply
current reduces to the sleep mode quiescent current.
Internal Linear Regulator (LDO)
The NCV8851−1 has an onboard low−dropout linear
regulator (LDO) internally connected to drive the low−side
gate. The 6VOUT pin should be externally connected to the
VIN_IC pin to power the internal rails. Typically, a RC filter
is used from 6VOUT to VIN_IC to further decrease noise on
the internal rails.
The 6VOUT pin should be externally connected through a
low leakage (< 100 mA at Tmax) diode to the BST pin,
charging the BST capacitor during off−time to generate a
voltage for the high−side driver. When the part is enabled
and VIN is below the LDO regulated value, the LDO is in
dropout and it tracks VIN. The LDO regulates its output once
VIN is above the output set point plus the dropout voltage.
An external bypass capacitor must be connected from
6VOUT to ground. A short to ground or overcurrent
condition on the 6VOUT pin will be mitigated by the LDO
current limit and internal thermal shutdown (TSD) circuitry
which disables all outputs. A normal soft−start will occur
when the die temperature falls below the TSD threshold.
Drivers
The NCV8851−1 includes 1.5 A gate drivers to switch
external N−Channel MOSFETs. This allows the
NCV8851−1 to address high−power, as well as low−power
conversion requirements. The gate drivers also include
adaptive non−overlap circuitry. The non−overlap circuitry
increases efficiency, which minimizes power dissipation, by
minimizing the body diode conduction time, while
protecting against cross−conduction (shoot−through) of the
MOSFETs. A detailed block diagram of the non−overlap
and gate drive circuitry used in the chip and related external
components is shown in Figure 23.
MainFault
GL to GH
Delay
PWM
Output
GH to GL
Delay
Main
Fault
GL
Threshold
VSW
Threshold
BST
GH
VSW
6VOUT
GL
PGND
VSW
Figure 23. Gate Driver Block Diagram
A capacitor is placed from VSW to BST and a diode is
placed from 6VOUT to BST to create a bootstrap supply on
the BST pin for the high−side floating gate driver. This
ensures that the voltage on BST is about 6VOUT higher than
VSW, less a diode drop, yielding a gate drive voltage high
enough to enhance the high−side MOSFET. The BST
capacitor supplies the charge used by the gate driver to
charge up the input capacitance of the high−side MOSFET,
and is typically chosen to be at least a decade larger than this
capacitance. A 0.1 mF BST capacitor is recommended.
Since the BST capacitor only recharges when the
low−side MOSFET is on, pulling VSW down to ground, the
NCV8851−1 has a minimum off−time. This also means that
the BST capacitor cannot be arbitrarily large, since 6VOUT
needs to be able to charge it up during this minimum
off−time so the high−side gate driver doesn’t run out of
headroom. 6VOUT needs to supply charge both to the BST
capacitor and also the low−side driver, so the LDO capacitor
must be sufficiently larger than the BST capacitor. A 1 mF
LDO capacitor is recommended.
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