ADM1062ASU データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
ADM1062ASU
Analog Devices
ADM1062ASU Datasheet PDF : 32 Pages
| |||
ADM1062
Preliminary Technical Data
Parameter
Min
Analog to Digital Converter
Signal Range
0
Input reference voltage on
REFIN pin, VREFIN
Resolution
INL
DNL
Gain Error
Offset Error
Input Noise
Buffered voltage output DACs
Resolution
Code 80h output voltage
Range 1
Range 2
Range 3
Range 4
Output voltage range
lsb step size
INL
DNL
Mid code error
Gain Error
Max Load Current (source)
Max Load Current(sink)
Max load Capacitance
Settling time into 50pF load3
Load regulation
PSRR3
80
Absolute Accuracy on any code
Reference Output
Reference Output
Max load current (source)
Max load current (sink)
Min load capacitance
Load regulation
PSRR3
Programmable Driver Outputs
High Voltage (Charge Pump)
Mode (PDO1-6)
Output Impedance
VOH
Ioutavg
Standard (Digital Output Mode
(PDO1-10)
VOH
2.044
100
75
11
10.5
Typ Max Unit Test Conditions/Comments
VREFIN
2.048 TBD
TBD
12
±1.5
±1
±2
±2
0.25
V
V
V
bits
lsb
lsb
lsb
lsb
lsbrms
The ADC can convert signals presented to the VH, VPn and
VX_GPIn pins.VPn and VH input signals are attenuated
depending on selected range. A signal at the pin corresponding
to the selected range will be between 0.573V and 1.375V at the
ADC input.
VDDCAP=2.7V
VDDCAP=4.75V
End-point corrected, VREFIN=2.048V
VREFIN = 2.048V
VREFIN = 2.048V
VREFIN = 2.048V
Direct input (no attenuator)
8
bits
6 DAC’s are individually selectable to be centered on one of four
output voltage ranges
0.6
V
0.8
V
1
V
1.25
V
601.25
mV
Same range independent of centre point
2.36
mV
0.25 lsb
0.2
lsb
0.5
lsb
0.4
%
100 µA
100 C
50
pF
2
µs
2.5
mV
per mA
dB
DC
40
dB
100mV step in 20ns with 50pF load
3
mV
2.048 2.052 V
200 µA
100 µA
nF
20
mA
dB
No Load
Cap required for decoupling, stability
per mA
DC
500
kΩ
12.5 14
V
IOH =0
12
V
IOH =1µA
20
µA
2V < VOH< 7V
2.4
V
VPU(Pullup to VDDCAP or VPN) = 2.7V, IOH = 0.5mA
Rev. PrJ | Page 6 of 32
Share Link: