ADM1062ASU データシートの表示（PDF） - Analog Devices
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ADM1062ASU
Analog Devices
ADM1062ASU Datasheet PDF : 32 Pages
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Preliminary Technical Data
ADM1062
Parameter
VOL
IOL
ISINK
RPULLUP
ISOURCE(VPn)
Tristate Output Leakage
Current
DIGITAL INPUTS (VXn,A0,A1)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
Programmable Pulldown
Current, IPULLDOWN
SERIAL BUS DIGITAL INPUTS
(SDA,SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL
SERIAL BUS TIMING
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tr
SCL, SDA Fall Time, tf
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Min
Typ Max Unit Test Conditions/Comments
4.5
V
VPU to Vpn = 6.0V, IOH = 0mA
VPU−0.3
V
VPU< = 2.7V, IOH = 1mA
0.1
V
IOL = 4mA
0.25 V
IOL = 10mA
0.5
V
IOL = 20mA
20
mA
Max sink current per PDO pin
60
mA
Max total sink for all PDOs
20
kΩ
Internal pullup
2
mA
Current Load on any VPn pull- ups (ie) total source current
available through any number of PDO pull-up switches
configured on to any one
10
µA
VPDO= 14.4V
2.0
V
Max. VIN=5.5V
0.8
V
Max. VIN=5.5V
−1
µA
VIN= 5.5V
1
µA
VIN= 0
TBD
pF
10
µA
If known logic state required
2.0
V
0.8
V
0.4
V
IOUT = -3.0mA
400 KHz
4.7
µs
4.7
µs
4
µs
4.7
µs
4
µs
1000 µs
300 µs
250
ns
300
ns
1 These are target specifications and subject to change.
2 At least one of the VH, VP1-4 pins must be ≥ 3.0V to maintain device supply on VDDCAP.
3 Guaranteed by Characterization.
4 Guaranteed by Design.
Rev. PrJ | Page 7 of 32
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