AT91M40800(2002) データシートの表示（PDF） - Atmel Corporation
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AT91M40800 Datasheet PDF : 19 Pages
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JTAG/ICE Debug
Memory Controller
Internal Memories
Boot Mode Select
Remap Command
1348DS–ATARM–02/02
AT91M40800
Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1
is connected to a device not including this pull-up, the user must make sure that a high
level is tied on NTRI while NRST is asserted.
ARM Standard Embedded In-circuit Emulation is supported via the JTAG/ICE port. The
pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be con-
nected to a host computer via the external ICE interface.
In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identi-
fies the microcontroller. This is not fully IEEE1149.1 compliant.
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes
the internal 32-bit address bus and defines three address spaces:
• Internal memories in the four lowest megabytes
• Middle space reserved for the external devices (memory or peripherals) controlled
by the EBI
• Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.
The AT91M40800 microcontroller integrates 8K bytes of internal SRAM. All internal
memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-
bit) or word (32-bit) accesses are supported and are executed within one cycle. Fetching
Thumb or ARM instructions is supported and internal memory can store twice as many
Thumb instructions as ARM ones.
The SRAM is mapped at address 0x0 (after the remap command), allowing ARM7TDMI
exception vectors between 0x0 and 0x20 to be modified by the software. The rest of the
bank can be used for stack allocation (to speed up context saving and restoring) or as
data and program storage for critical algorithms.
The ARM reset vector is at address 0x0. After the NRST line is released, the
ARM7TDMI executes the instruction stored at this address. This means that this
address must be mapped in nonvolatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of
the NRST selects the type of boot memory (see Table 3).
The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like
any standard PIO line.
Table 3. Boot Mode Select
BMS
Boot Memory
1
External 8-bit memory on NCS0
0
External 16-bit memory on NCS0
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction,
Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to
allow these vectors to be redefined dynamically by the software, the AT91M40800
microcontroller uses a remap command that enables switching between the boot mem-
ory and the internal primary SRAM bank addresses. The remap command is accessible
through the EBI User Interface, by writing one in RCB of EBI_RCR (Remap Control
Register). Performing a remap command is mandatory if access to the other external
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