DS1330WP-100 データシートの表示（PDF） - Maxim Integrated
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DS1330WP-100 Datasheet PDF : 10 Pages
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POWER-DOWN/POWER-UP TIMING
PARAMETER
SYMBOL MIN
VCC Fail Detect to CE and
WE Inactive
tPD
VCC slew from VTP to 0V
VCC Fail Detect to
RST Active
tF
150
tRPD
VCC slew from 0V to VTP
tR
150
VCC Valid to CE and
WE Inactive
tPU
VCC Valid to End of
Write Protection
tREC
VCC Valid to RST Inactive
tRPU
150
VCC Valid to BW Valid
tBPU
TYP
200
DS1330W
(TA: See Note 10)
MAX UNITS NOTES
1.5
µs
11
µs
15
µs
14
µs
2
ms
125
ms
350
ms
14
1
s
14
BATTERY WARNING TIMING
PARAMETER
SYMBOL
Battery Test Cycle
Battery Test Pulse Width
Battery Test to BW Active
tBTC
tBTPW
tBW
MIN
(TA: See Note 10)
TYP MAX UNITS NOTES
24
hr
1
s
1
s
PARAMETER
Expected Data
Retention Time
SYMBOL
tDR
MIN
10
(TA= +25°C)
TYP MAX UNITS NOTES
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = VIH or VIL . If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output
buffers remain in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
8 of 10
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