HYB3164805BJ-50 データシートの表示（PDF） - Siemens AG

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HYB3164805BJ-50

8M x 8-Bit Dynamic RAM (4k & 8k Refresh, EDO-version)

Siemens AG 

HYB3164(5)805BJ/BT(L)-40/-50/-60

8M x 8-DRAM

AC Characteristics (cont’d) 5)6)

TA = 0 to 70 °C,VCC = 3.3 V ± 0.3V , tT = 2 ns

AC64-2E

Parameter

Symbol

- 40

Limit Values

- 50

- 60

Unit Note

min. max. min. max. min. max.

RAS pulse width in hyper page mode tRAS

CAS precharge to RAS Delay

tRHPC

OE pulse width

tOEP

OE hold time from CAS high

tOEHC

Output buffer turn-off delay from WE tWEZ

OE setup time prior to CAS

tOES

40 200k 50 200k 60 200k ns

22 – 27 – 32 – ns

5 – 5 – 5 – ns

5 – 5 – 5 – ns

0 10 0 13 0 15 ns

5 – 5 – 5 – ns

Hyper Page Mode (EDO) Read-

modify-Write Cycle

Hyper page mode (EDO) read-write tPRWC

cycle time

44 – 54 – 63 – ns

CAS precharge to WE

tCPWD 34 – 42 – 49 – ns

CAS before RAS Refresh Cycle

CAS setup time

tCSR

CAS hold time

tCHR

RAS to CAS precharge time

tRPC

Write to RAS precharge time

tWRP

Write hold time referenced to RAS tWRH

5 – 5 – 5 – ns

5 – 5 – 10 – ns

5 – 5 – 5 – ns

5 – 5 – 10 – ns

5 – 5 – 10 – ns

Self Refresh Cycle (L-versions only)

RAS pulse width

RAS precharge time

CAS hold time

tRASS

tRPS

tCHS

100k

100k _ 100k _

69 – 84 – 104 –

-50 – -50 – -50 –

ns 17

ns 17

ns 17

Test Mode Cycle

Write command setup time

Write command hold time

tWTS

5 – 5 – 5 – ns 18

tWTH

5 – 5 – 5 – ns 18

Semiconductor Group

11

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