AV9176M-01 データシートの表示（PDF） - Integrated Circuit Systems

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コンポーネント説明

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AV9176M-01

Low Skew Output Buffer

Integrated Circuit Systems 

Timing Diagrams

Timing in Divide by 1 Mode

ICS9176-01

Timing in Divide by 2 Mode

Timing in Eliminate by Test Mode

Note: In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is transparent. Damage

to the device may occur if an output is shorted or forced to ground or VDD.

Timing in Power-down Mode

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