ISPLSI2192VL-100LT128(2000) データシートの表示（PDF） - Lattice Semiconductor

部品番号

コンポーネント説明

メーカー

ISPLSI2192VL-100LT128
(Rev.:2000)

2.5V In-System Programmable SuperFAST™ High Density PLD

Lattice Semiconductor 

Specifications ispLSI 2192VL

Functional Block Diagram

Figure 1. ispLSI 2192VL Functional Block Diagram

RESET

GOE 0

GOE 1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN

95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 11* 10

I/O I/O I/O I/O I/O I/O I/OI/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 9 8

Generic

Logic Blocks

(GLBs)

A0

A1

A2

A3

A4

A5

A6

A7

Input Bus

Output Routing Pool (ORP)

F7 F6 F5 F4 F3 F2 F1 F0

Input Bus

Output Routing Pool (ORP)

E7 E6 E5 E4 E3 E2 E1 E0

D7

D6

D5

Global

D4

Routing

Pool

D3

(GRP)

D2

D1

D0

IN 7/TCK

IN 6/TDO

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

TDI/IN 0

TMS/IN 1

B0 B1 B2 B3 B4 B5 B6 B7

C0 C1 C2 C3 C4 C5 C6 C7

Megablock

BSCAN

Output Routing Pool (ORP)

Input Bus

IN 2* IN 3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

*Note: Dedicated Inputs 2, 5 and 11 are not available with 128-pin packages.

Output Routing Pool (ORP)

Input Bus

IN4 IN 5* I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Y0 Y1 Y2

2192VL Block.eps

The 2192VL contains 96 I/O cells. Each I/O cell is directly

connected to an I/O pin and can be individually pro-

grammed to be a combinatorial input, output or

bi-directional I/O pin with 3-state control, and the output

drivers can source 4mA or sink 8mA. Each output can be

programmed independently for fast or slow output slew

rate to minimize overall output switching noise. Device

pins can be safely driven to 3.3V signal levels to support

mixed-voltage systems.

Eight GLBs, 16 I/O cells, two dedicated inputs and an

ORP are connected together to make a Megablock (see

Figure 1). The outputs of the eight GLBs are connected

to a set of 16 universal I/O cells by the ORPs. Each ispLSI

2192VL device contains six Megablocks.

The GRP has as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 2192VL device are selected using

the dedicated clock pins. Three dedicated clock pins (Y0,

Y1, Y2) or an asynchronous clock can be selected on a

GLB basis. The asynchronous or Product Term clock can

be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the

outputs of the ispLSI 2192VL are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. The default configuration is a totem-pole

configuration. The open-drain/totem-pole option is se-

lectable through the ispDesignEXPERT software tools.

2

Share Link: