RMLA3565-53 データシートの表示（PDF） - Raytheon Company
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RMLA3565-53 Datasheet PDF : 5 Pages
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RMLA3565-53
Wideband Low Noise MMIC Amplifier
Application Information
CAUTION: THIS IS AN ESD SENSITIVE DEVICE
The following briefly describes a procedure for evaluating the high efficiency PHEMT amplifier packaged
in a surface mount package. It may be noted that the chip is a fully monolithic single ended two stage
amplifier for 3.5 to 6.5 GHz applications. Figure 1 shows the functional block diagram of the packaged
product.
Test Fixture
Figure 2 shows the outline and pin-out descriptions for the packaged device. A typical test fixture
schematic showing external bias components is shown in figure 3. Figure 4 shows typical layout of an
evaluation board corresponding to the schematic diagram. A typical performance obtained from the test
fixture is shown in figure 5. The following should be noted:
(1) Package pin designations are as shown in figure 2.
(2) Vd is the Drain Voltage (positive) applied at the pins of the package
(3) Vdd is the positive supply voltage at the evaluation board terminal
Test Procedure for the evaluation board (RMLA3565-53-TB)
The following sequence of procedure must be followed to properly test the power amplifier:
Step 1: Turn off RF input power.
Step 2: Use GND terminal of the evaluation board for DC supplies.
Step 3: Apply drain supply voltages of +4.0 V to evaluation board terminals Vdd.
Step 4: After the bias condition is established, RF input signal may now be applied.
Step 5: Follow turn-off sequence of:
(i) Turn off RF Input Power (ii) Turn down and off Vdd
Figure 3. Schematic for a Typical Test Evaluation Board (RMLA3565-53-TB)
RF in
J1
RF out
J2
GRND
P2
C2
(OPT) C3
Vdd
C1
P1
Characteristic performance data and specifications are subject to change without notice.
Tel: 978-470-9715
FAX: 978-470-9452
www.raytheon.com/micro
Revised July 30, 1999
Page 3
Raytheon RF Components
362 Lowell Street
Andover, MA 01810
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