TSL2550 データシートの表示（PDF） - austriamicrosystems AG
部品番号
コンポーネント説明
メーカー
TSL2550 Datasheet PDF : 21 Pages
| |||
TSL2550
AMBIENT LIGHT SENSOR
WITH SMBus INTERFACE
TAOS029L − OCTOBER 2007
Command Register
The command register is used primarily to:
D Select which ADC register will be read during a read cycle
D Switch the dynamic range of the device between standard and extended range modes
D Power the device up for operation or power it down for minimum power consumption
Table 1 shows the six primary commands used to control the TSL2550.
lid COMMAND
0x00h
a 0x03h
0x1Dh
v 0x18h
ill 0x43h
0x83h
Table 1. Command Summary
FUNCTION
Power-down state
Power-up state/Read command register
Write command to assert extended range mode
Write command to reset or return to standard range mode
Read ADC channel 0
Read ADC channel 1
t The content of the command register defaults to 0x00h when power is applied to the device, placing the device
G s into the power-down mode.
Once the TSL2550 is set to the standard range mode (0x18h) or the extended range mode (0x1Dh), the device
A t remains in that mode until it is powered down or the mode is changed via the command register.
s n The 0x03h command has two purposes: It is used to power up the device and can also be used to check that
the device is communicating properly. The value returned during a read cycle should be 0x03h.
m te ADC Register
a n The TSL2550 contains two ADC registers (channel 0 and channel 1). Each ADC register contains two
component fields that are used to determine the logarithmic ADC count value: CHORD bits and STEP bits. The
o CHORD bits correspond to the most significant portion of the ADC value and specifies a segment of the
piece-wise linear approximation. The STEP bits correspond to the least significant portion of the ADC count
c value and specifies a linear value within a segment. CHORD and STEP bits all equal to 0 corresponds to a
condition in which the light level is below the detection limit of the sensor. CHORD and STEP bits all equal to
l 1 corresponds to an overflow condition.
a Each of the two ADC value registers contain seven data bits and a valid bit as described in Table 2.
icTable 2. ADC Register Data Format
VALID
CHORD BITS
STEP BITS
n B7
B6
B5
B4
B3
B2
B1
B0
VALID
C2
C1
C0
S3
S2
S1
S0
ch FIELD
VALID
TeCHORD
BITS
7
6 to 4
DESCRIPTION
ADC channel data is valid. One indicates that the ADC has written data into the
channel data register, since ADCEN was asserted in the COMMAND register.
CHORD number.
STEP
3 to 0 STEP number.
Copyright E 2007, TAOS Inc.
8
r
www.taosinc.com
The LUMENOLOGY r Company
r
Share Link: 