CY7C1020CV33-15ZSXE(2010) データシートの表示（PDF） - Cypress Semiconductor

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CY7C1020CV33-15ZSXE
(Rev.:2010)

512 K (32 K × 16) Static RAM

Cypress Semiconductor 

CY7C1020CV33

Switching Waveforms

Read Cycle No. 1[9, 10]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Read Cycle No. 2 (OE Controlled)[10, 11]

DATA VALID

ADDRESS

CE

OE

BHE, BLE

DATA OUT

VCC

SUPPLY

CURRENT

tRC

tACE

tDOE

tLZOE

tDBE

tLZBE

HIGH IMPEDANCE

tLZCE

tPU

50%

DATA VALID

tHZOE

tHZCE

tHZBE

HIGH

IMPEDANCE

tPD

50%

IICCCC

IISSBB

Notes

9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.

10. WE is HIGH for Read cycle.

11. Address valid prior to or coincident with CE transition LOW.

Document Number: 38-05133 Rev. *H

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