AFCT-5943XXZ データシートの表示（PDF） - Avago Technologies

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AFCT-5943XXZ

Single Mode SFF Transceivers for SONET OC-48/SDH STM-16 Multirate Operation

Avago Technologies 

Functional Description

Receiver Section

Design

The receiver section for the AFCT-5943xxZ contains an

InGaAs/InP photo detector and a preamplifier mounted

in an optical subassembly. This optical subassembly

is coupled to a postamp/decision circuit on a circuit

board. The design of the optical assembly is such that it

provides better than 27 dB Optical Return Loss (ORL).

The postamplifier is ac coupled to the preamplifier as

illustrated in Figure 1. The coupling capacitors are large

enough to pass the SONET/SDH test pattern at 155 Mb/

s, 622 Mb/s and 2488 Mb/s without significant distor-

tion or performance penalty. For multirate applications

the sensitivity will meet the maximum SONET specifica-

tion for OC48 across all datarates (-19 dBm), also for DC

balanced codes, e.g. 8B/10B. For codes which have a

significantly lower frequency content, jitter and pulse

distortion could be degraded.

The receiver outputs are squelched at Signal Detect

deasserts. That is, when the light input decreases to

typical -27 dBm or less, the Signal Detect deasserts i.e.

the SD Output goes to a PECL low state. This forces the

DATA OUT and DATA OUT Bar to go PECL levels high

and low respectively.

Figure 1 also shows a filter function which limits the

bandwidth of the preamp output signal. The filter is de-

signed to bandlimit the preamp output noise and thus

improve the receiver sensitivity.

These components will reduce the sensitivity of the re-

ceiver as the signal bit rate is increased above 2.7 Gb/s.

Noise Immunity

The receiver includes internal circuit components to

filter power supply noise. However under some condi-

tions of EMI and power supply noise, external power

supply filtering may be necessary (see Application Sec-

tion).

The Signal Detect Circuit

The signal detect circuit works by sensing the peak level

of the received signal and comparing this level to a ref-

erence. The SD output is low voltage TTL.

TRANS-

IMPEDANCE

PRE-

AMPLIFIER

FILTER

AMPLIFIER

PECL

OUTPUT

BUFFER

DATA OUT

DATA OUT

GND

Figure 1. Receiver Block Diagram

SIGNAL

DETECT

CIRCUIT

TTL

OUTPUT

BUFFER

SD



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