M24C01(2000) データシートの表示（PDF） - STMicroelectronics
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M24C01 Datasheet PDF : 20 Pages
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M24C16, M24C08, M24C04, M24C02, M24C01
Table 2. Absolute Maximum Ratings 1
Symbol
Parameter
TA
Ambient Operating Temperature
TSTG
Storage
Temperature
TLEAD
Lead Temperature
during Soldering
VIO
Input or Output range
VCC
Supply Voltage
Value
Unit
-40 to 125
°C
-65 to 150
°C
PSDIP8: 10 sec
260
SO8: 40 sec
215
TSSOP8: 40 sec
215
°C
SBGA5: t.b.c.
t.b.c.
-0.6 to 6.5
V
-0.3 to 6.5
V
VESD
Electrostatic Discharge Voltage (Human Body model2)
4000
V
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
These memory devices are compatible with the
I2C memory standard. This is a two wire serial
interface that uses a bi-directional data bus and
serial clock. The memory carries a built-in 4-bit
unique Device Type Identifier code (1010) in
accordance with the I2C bus definition.
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory
inserts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until the VCC voltage has reached
the POR threshold value, and all operations are
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC
20
16
12
8
4
0
10
fc = 100kHz
fc = 400kHz
100
CBUS (pF)
RL
SDA
MASTER
SCL
RL
CBUS
1000
CBUS
AI01665
3/20
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