M24C01(2000) データシートの表示（PDF） - STMicroelectronics
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M24C01 Datasheet PDF : 20 Pages
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
WC
BYTE WRITE
ACK
ACK
ACK
DEV SEL
BYTE ADDR
DATA IN
R/W
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
ACK
ACK
ACK
ACK
DEV SEL
BYTE ADDR DATA IN 1
DATA IN 2
DATA IN 3
R/W
ACK
ACK
DATA IN N
AI02804
capacity of 16 Kbits, 2 KBytes (except where
M24C01 devices are used).
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding
memory gives an acknowledgment on the SDA
bus during the 9th bit time. If the memory does not
match the Device Select Code, it deselects itself
from the bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for an address byte. The memory
responds to the address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the address byte) will not
modify the memory contents, and the
accompanying data bytes will not be
acknowledged (as shown in Figure 5).
Byte Write
In the Byte Write mode, after the Device Select
Code and the address, the master sends one data
byte. If the addressed location is write protected by
the WC pin, the memory replies with a NoAck, and
the location is not modified. If, instead, the WC pin
has been held at 0, as shown in Figure 6, the
memory replies with an Ack. The master
terminates the transfer by generating a STOP
condition.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single write cycle, provided that they
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