LTC2912CTS83 データシートの表示（PDF） - Analog Devices
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LTC2912CTS83 Datasheet PDF : 14 Pages
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LTC2912
APPLICATIONS INFORMATION
The rise time on the UV, OV and 0V pins is limited by a 400k
pull-up resistance to VCC. A similar formula estimates the
output rise time (10% to 90%) at the UV, OV and OV pins:
tRISE ≈ 2.2 • RPU • CLOAD
where RPU is the pull-up resistance.
OV/OV Latch (LTC2912-1, LTC2912-3)
With the LATCH pin held low, the OV pin latches low
(LTC2912-1) and the OV pin latches high (LTC2912-3)
when an OV condition is detected. The latch is cleared
by raising the LATCH pin high. If an OV condition clears
while LATCH is held high, the latch is bypassed and the
OV and OV pins behave the same as the UV pin with a
similar timeout period at the output. If LATCH is pulled
low while the timeout period is active, the OV and OV pins
latch as before.
Disable (LTC2912-2)
The LTC2912-2 allows disabling the UV and OV outputs via
the DIS pin. Pulling DIS high forces both outputs to remain
weakly pulled high, regardless of any faults that occur on
the inputs. However, if a UVLO condition occurs, UV as‑
serts and pulls low, but the timeout function is bypassed.
UV pulls high as soon as the UVLO condition is cleared.
DIS has a weak 2µA (typical) internal pull-down current
guaranteeing normal operation with the pin left open.
TYPICAL APPLICATIONS
Dual UV/OV Supply Monitor, 3.3V ±10% Tolerance
POWER 3.3V
SUPPLY
CBYP 0.1µF
RC
27.4k 2
RB
1k 3
RA
4.53k
1
VCC
6
VH
OV
LTC2912-1
VL
7
UV
8
LATCH
GND TMR
5
4 CTMR
22nF
SYSTEM
2912 TA02
TIMEOUT = 200ms
48V Supply Monitor (<±10% = Powergood)
POWER
SUPPLY
48V
CBYP
0.1µF
RZ
200k
RC
1
37.4M 2
VCC
6
VH
OV
RB
80.6k 3
LTC2912-2
7
VL
UV
RA
357k
8
DIS
GND TMR
RPG
30k
POWERGOOD
LED
5
4
CTMR
10nF
TIMEOUT = 85ms
2912 TA03
Dual UV Supply Monitor, 3.3V, 2.5V, 10% Tolerance
3.3V
POWER
SUPPLIES
2.5V
CBYP 0.1µF
RB1
54.9k
RB2
39.2k
1
4
2 VCC
VH
TMR 6
OV
RA1
LTC2912-2
11k
7
UV
3
VL
8
DIS
RA2
GND
11k
5
RUV
ROV 10k
10k
SYSTEM
2912 TA04
For more information www.analog.com
Rev. C
11
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