LT1374CFE データシートの表示（PDF） - Linear Technology
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LT1374CFE Datasheet PDF : 32 Pages
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LT1374
BLOCK DIAGRA
INPUT
BIAS*
2.9V BIAS
REGULATOR
INTERNAL
VCC
0.01Ω
+–
CURRENT
SENSE
AMPLIFIER
VOLTAGE GAIN = 20
SLOPE COMP
Σ
SYNC
SHUTDOWN
COMPARATOR
500kHz
OSCILLATOR
0.9V
CURRENT
COMPARATOR
+
S
RS
FLIP-FLOP
R
–
SHDN
0.4V
3.5µA
+
FOLDBACK
CURRENT Q2
LIMIT
CLAMP
–
LOCKOUT
COMPARATOR
VC
2.38V
*BIAS PIN IS AVAILABLE ONLY ON THE S0-8 AND FE16 PACKAGES
FREQUENCY
SHIFT CIRCUIT
ERROR
AMPLIFIER
gm = 2000µMho
Figure 1. Block Diagram
BOOST
DRIVER
CIRCUITRY
Q1
POWER
SWITCH
VSW
2.42V
FB
GND
1374 BD
APPLICATIO S I FOR ATIO
FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1374 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
foldback frequency and current limiting created by the FB
pin. Please read both parts before committing to a final
design. The fixed 5V LT1374-5 has internal divider resis-
tors and the FB pin is renamed SENSE, connected directly
to the output.
The suggested value for the output divider resistor (see
Figure 2) from FB to ground (R2) is 5k or less, and a
formula for R1 is shown below. The output voltage error
caused by ignoring the input bias current on the FB pin is
less than 0.25% with R2 = 5k. A table of standard 1%
values is shown in Table 1 for common output voltages.
8
Please read the following if divider resistors are increased
above the suggested values.
Table 1
OUTPUT
R1
% ERROR AT OUTPUT
VOLTAGE
R2
(NEAREST 1%) DUE TO DISCREET 1%
(V)
(kΩ)
(kΩ)
RESISTOR STEPS
3
4.99
1.21
+ 0.23
3.3
4.99
1.82
+ 0.08
5
4.99
5.36
+ 0.39
6
4.99
7.32
– 0.5
8
4.99
11.5
– 0.04
10
4.99
15.8
+ 0.83
12
4.99
19.6
– 0.62
15
4.99
26.1
+ 0.52
1374fd
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